Vybrid low power wakup source

[LinhNguyen]

Hi,

I have a problem with Vybrid wakeup. Problem was detailed following. I use Linux with TimeSys LinuxLink factory.

Case 1: run Linux only - Core M4 does not run

#1: I configure GPC IMR registers to unmask CAN0, SW1 wakeup source, configure CCM_CCGR to enable CAN0, SW1 clock in stop mode. After that I enter stop mode by command "echo mem > /sys/power/state", then I can wake up the board by send any CAN0 message or press SW1.

#2: I configure GPC IMR register to unmask SW1 wakeup source only. In this case, only SW1 can wakeup the board from stop mode. This is as I expected from Reference Manual.

Case 2: run both Linux on A5 & bare metal code on M4

#3: On core M4 I run an empty code while 1 loop after startup. On A5 I run Linux with #2 configuration. In this case I can wakeup A5 by any method (Send CAN0 message, press SW1). I expect that only SW1 can wakeup the board in this case.

I guest if Vybrid run both core, it can wakeup from stop mode BY ANY INTERRUPTS. It seem wrong compare to Reference Manual.

Please help me to correct case #3, I want the board only wakeup by SW1 pressed at this case.

Thanks & Regards,

Linh Nguyen

[naoumgitnik]

Dear richard_stulens,

If I am not wrong, you might have a sample code for this case.

Please, feel free to comment in this thread as well.

Thanks in advance, Naoum Gitnik.

[LinhNguyen]

Dear timesyssupport and all,

I can not attach FlexCAN code here. But I have tried with latest TimeSys kernel <commit b2faeb5472fe71b505a103388b8a8540dbd47134>, and modify file arch/arm/mach-mvf/system.c like this:

void gpc_set_wakeup(void)

{

    __raw_writel(0xffffffff, gpc_base + GPC_IMR1_OFFSET);

    __raw_writel(0xffffffff, gpc_base + GPC_IMR2_OFFSET);

    __raw_writel(0xffffffff, gpc_base + GPC_IMR3_OFFSET);

    __raw_writel(0xffffffff, gpc_base + GPC_IMR4_OFFSET);

    return;

}

Expectation is the board does not wake up from stop mode by button SW1 with this modification. But it does.

test step:

s1: # echo 'mem' > /sys/power/state

s2: press SW1

I have tried with the kernel & rootfs version of Demo OOBE (Embedded Linux software, platform, distributions, packages, libraries, development and debugging too...), with the same modification. And the same problem occurs.

Can you please confirm is that hardware problem or not?

[richard_stulens · Accepted solution]

Hi Linh,

I think you must also stop the M4 core ("WFI" instruction) before the chip will enter stop mode. i.e. Both cores must be waiting on a WFI instruction.

When one of the cores is still running, any interrupt that is routed to the stopped core will wake it up (from WFI).

Please give that a try and let us know if that solved your problem.

Best regards,

Richard

[LinhNguyen]

Dear Richard,

I have tried, It seems you are right. The Vybrid SOC is in stop mode when both of cores in "WFI" instruction.

Thank Richard, TimeSys and Naoum.

[naoumgitnik]

(updated)

Dear Linh,

Are we talking about the "Stop" or the "LPStop" mode, please?

If the "Stop" mode, the code in the [MQX LOWPOWER] Issue with CAN wakeup source on STOP mode thread might be useful.

Regards, Naoum Gitnik.

[timesyssupport]

Hi Naoum, richard_stulens,

The scenario Linh describes above is using Stop mode, as the Linux kernel is configured to enter Stop mode after the command 'echo mem > /sys/power/state' is executed. Also, I have reproduced this with the M4 core not running, just Linux on the A5 core: after masking the four IMR registers, the Vybrid is still able to resume from Stop mode after pressing SW1. Are you aware of any condition that would allow the Vybrid to resume, even with the four IMR registers masked?

edit: This is may be because, although the M4 core had not started, it was not explicitly in stop mode with the 'WFI' instruction.

Thanks,

Timesys Support