IMX.6 Dual/Quad parallel camera port 20bits mode

[michalkaczmarek]

Hello everybody

I have a question about CSI camera parallel interface.
The document IMXDQRM in Section 1.4, 9.2.1.1, 37.3.1.1 is written that a parallel camera interface is up to 20 bits.

But in Section 37.4.3.2.1 is written:

37.4.3.2.1 Parallel Interface
In parallel interface a single value in each clock arrives, except when working in BT.1120
mode, In Which two values ​​arrive in each cycle. Each value can be 8-16 bit wide
According to configuration of DATA_WIDTH. If DATA_WIDTH is configured to N,
then 20-N LSB bits are ignored.

Is it possible to work with this interface so that you can receive a 20-bit words? If so, how to configure the interface?

Michal

[SergioSolis]

Hello Michal,

No, you cannot use the parallel port in 20bit mode, you can only use it in 16bit mode.

[ivankozic]

If so, then both the RM and DS are wrong - not to mention that hardware has 20-bit interface. There is conflicting information all over the i.MX6 documentation for some reason. By the way the IPU driver and V4L driver both include support for 10-bit mode (in bt.1120 20-bit). For instance:
- DS page 96-97 clearly state that you can use YCbCr mode of 20-bit width, there is even a mapping table on page 96 (chapter 4.11.10.1 IPU Sensor Interface Signal Mapping), page 97 states that you can use 20-bit mode for bt.1120 and that 16-bit mode is actually a SUB-CASE of 20-bit mode in which corresponding LSBs are ignored,

- RM is a different story: Table 37-2 on page 2695 clearly states that you can use bt.1120 in 20-bit mode, the only problem being that it doesn't support on-the-fly processing. This is the first problem, as the same table states that on-the-fly processing is supported for bt.1120 in 16-bit mode. This is Conflict #1 - this implies that 16-bit bt.1120 is NOT SUB-CASE of 20-bit bt.1120.
- Further investigation leads us to the page 2761, where it states that CCIR commands should be set with using CCIR_CODE_1, CCIR_CODE_2 and CCIR_PRECOM register. The third one does not exist and is called CCIR_CODE_3 instead. Bear in mind that this is quite, quite a buggy document. FYI CCIR commands are actually EAV and SAV codes.

- If we go yet further to the memory map to the fore-mentioned CCIR_CODE_3 register (page 3252), we'll see that there is a clear distinction between 8-bit/value and 10-bit/value CCIR commands, as when using bt.656 we should use 3x8bit while for bt.1120 we should use 3x10-bit to describe the first three words of EAV and SAV.
- Also, to find info about how to really set up CCIR_CODE_1 and CCIR_CODE_2, you'll have to search the Community a bit as most is not documented.
So, with all respect to SerchMX, either he is not really sure what he's saying or Freescale documentation is even worse than it looks. Either way, FYI making this whole thing work is a big and ugly job, as most drivers are also only half-written, although you'll get a lot of support from the Community.
For instance, I have set everything just fine, rewritten the bad IPU and V4L drivers and I still don't get an image for bt.1120. And I have worked with a lot of MCUs, some SoCs and plenty of FPGAs. This is by far the worst documentation I have ever seen.
Just my 2 cents...

[phil_martin]

We are trying to get the camera inputs running and have similar problems

- we're sending video from an FPGA to the CPU using 10-bit buses with embedded syncs (TRSs)

- the video is HD not SD, but since we're using a multiplexed UYVY bus, we should use the BT656 mode rather than the BT1120 Mode, right?

- but since the video is 10-bit, not 8-bit, should we use 8-bit or 10-bit TRS codes in CODE_3? (i.e. 0xFF0000 or 0x3FF00000 (or 0x3FC00000) )??

The  RM states

"

For BT.656 the code should be written to bits [23:0] while bits [29:24] are ignored (3X8bit)

For BT.1120 the code should be written to bits [29:0] (3X10bit)

"
- but does this depend on the BT656/BT1120 selection or the 8-bit data / 10-bit data selection ?

[nagendrasarma]

hi Freescale

we have similar requirement

we are trying to give hd input (1080p@30) through BT1120 (BT656 clk*2 8bit) to imx (imx support BT.1120 page 2699 IMX6DQRM.pdf)

we would like to know the feasibility and some hw ans sw reference designs

regards

Nagendra

[michalkaczmarek]

Thank You SerchMX.

I have three questions.

1. What is the purpose of the physical 20-bit interface, if you can only receive 8-16-bit data.

2. In the document IMXDQRM in Table 37-2 it is written:

     ...

     In parallel I/F: through a 10-bit

     bus (such as BT.656) or 20-bit

     bus (such as BT.1120).

What does it mean?

3. Is it possible to read 20-bit data as 'generic data'?

Michal.