Question:
On i.MX6 DQ, the ON_TIME and DEBOUNCE bit fields of the SNVS_LPCR register are not readable. Also in the preliminary (i.MX61) specs bits 31-15 are reserved. Are ON_TIME and DEBOUNCE bit fields actually in this register for i.MX 6DQ and are these bits writable but not readable?
Answer:
This is a document issue which will be fixed in the next version of the RM. The register diagram should read as follows:
