The feature Fraction Delay logic with Micro-Edge Placement for eFlexPWM module

Document created by xiangjun.rong Employee on Jul 16, 2015Last modified by ebiz_ws_prod on Dec 13, 2017
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For switch mode power supply application, the output voltage resolution is dependent on PWM resolution, the PWM resolution is dependent on the PWM module driving clock(IP Bus clock) frequency and PWM signal output frequency.  But the eflexPWM module has a new feature Fraction Delay logic with Micro-Edge Placement, which is equivalent to increase the PWM module driving clock frequency, accordingly increase the PWM resolution.

For the MC56F84xxx, there are two eFlexPWM modules: eFlexPWMA  and eFlexPWMB, the eFlexPWMA supports fractional Delay logic with micro-edge placement. For MC56F82xxx, there is only one eFlexPWMA module. The eFlexPWMA  module has an internal PLL which can multiply the PWM driving clock frequency by 32. For example, for the MC56F84789, the PWM driving clock frequency is 100MHz, the internal PLL of eFlexPWM module can output a clock frequency 32*100MHz=3.2GHz, so the PLL clock cycle is 312pS, in other words, the fractional cycle time of eFlexPWM is 312pS.

For the eFlexPWM module, the eFlexPWMA_SM0 counter counts tick from the value of PWMA_SM0_INIT to  the value of PWMA_SM0VAL1 register, the main duty cycle of PWMA_A0 signal is controlled by PWMA_SM0VAL2(rising edge) and PWMA_SM0VAL3(falling edge), the main duty cycle of PWMA_B0 signal is controlled by PWMA_SM0VAL4(rising edge) and PWMA_SM0VAL5(falling edge). The new feature Fraction Delay logic with Micro-Edge Placement of eFlexPWM can place the rising or falling edge with fractional cycle time, which increase the PWM resolution by 5 bits.

The demo code demonstrates the feature of Fraction Delay logic with Micro-Edge Placement  the eFlexPWM. The SM0 module outputs two channels PWMA_A0 and PWMA_B0. This is the configuration:for

PWMA_SM0VAL2= PWMA_SM0VAL4=0xfffd, PWMA_SM0VAL3= PWMA_SM0VAL5=0x03, and PWMA_SM0CTRL2=0x2000;




From the above configuration, the PWMA_A0 and PWMA_B0 are in independent mode and the main duty cycle is the same. But PWMA_SM0FRACVAL3 is assigned with 0xF000, so the falling edge of PWMA_A0 will have a fractional placement as the following figure.

The code is developed under CodeWarrior for microcontroller ver 10.6 and processor Expert, TWR-8200 board.


In the above figure, the there are two channels which are superimposed together so that user can compare the timing.

The channel1(yellow trace) is the PWMA_A0 signal with a fractional edge placement which is connected to pin9 of J510 on TWR-8200 board. The Channel2(pink trace) is PWMA_B0, which does not have fractional edge placement and connected to pin11 of J510.


XiangJun Rong

Original Attachment has been moved to: HRpwm82748.rar