DRAM Controller Optimization for i.MX Application Processors

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The training will focus on the DDR controller used in the i.MX53 and i.MX6 series processors. It will include operation, register programming and calibration techniques to properly tune the various DDR types supported: LPDDR2, DDR2 and DDR3. Hardware layout considerations will also be discussed.

 

Presented by Mark Middleton

Presented at DwF Silicon Valley - March 26, 2015

Session ID: AMF-DES-T1060

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