Loss of data on RGMII bus between 8548E and Marvell 88E1111

[Willem]

We are using a MPU8548E with a Marvell 88E1111 PHY, using RGMII to communicate with the two.  We are running at 2.5 MHz (10 Mbps) to debug this problem. We are using u-boot as the OS. 

When we send out a ping command (72 bytes) we find that the PHY only sends out 71 bytes over the SERDES to the transciever, missing the last byte.  We are using  a logic analzyer and have the PHY in loop-back mode to monitor both the Tx signals to the PHY and Rx signal from the PHY to the PPC.  Using the logic analyzer we have confirmed we send out the correct data to the PHY and we recieve the correct data back execpt for the last byte.  We are assuming somehow the PHY does not read in the last byte, however looking that the signals with an oscilloscope the TSEC1_TX_EN (TX_CTL) line stays high during the entire transmission and is the correct length (57.6 us = 72  bytes* 2 clocks per byte * .4 us clock period). 

This issue may well be with the Marvell PHY.  My question is if there is anyway to extend the TSEC1_TX_EN signal, or if anyone else has encountered this problem, to us the data seems like it should be valid.

I have included a link to screen grab of the logic analyzer.  The top bus the Tx to the PHY, note the data stream is: 61 4E 55 FC  the bottom bus that is slightly delayed is the Rx from the PHY, note that the data stream is the same, but missing the last byte: 61 4E 55 __   

Link to Screen Grabs of Logic Analyzer

thanks for any help !

Logic Analyzer - Missing Last byte.png

Message Edited by t.dowe on 2009-08-31 11:53 AM

[Willem · Accepted solution]

Problem Solved!

As described we were missing the last set of data.  If we added a delay on the Marvell PHY our data was corrupted.  This indicated that there was a timing error of some sort; either the data was captured too late and we missed the last byte, or when we added the delay in the Marvell the data became corrupted because we must have been right at the edge of the data transistions.  (as far as we know there is no way to control the delay on the Marvell, and we don't actually know the amount of delay it sets)

The problem was solved by adding a delay line on the clock signal.  We ended up using a long loop of co-ax cable on the clock line and this delayed it by several nano seconds, enough for the data to be correctly read in.  We were working at 10 Mbs, so to make it work at 125 MHz (1 Gbps) might be tricky.  The original error is in the layout.  Hope this is helpful to people with similiar problems.

Message Edited by Willem on 2009-08-28 01:29 AM

[oded_asulin]

Hi,

I am not sure it's the same. but i had problems (CRC errors, TX threshold) while working on 1Gb with this phy.

please check, if you are working with 1Gb (in your normal mode, not on this debug mode), the seriel resistor on the 125MHZ clock, i found that the value of 22 ohm in my design was high and after reducing the res value, thing stated to work out.

good luck