S32K142 & S32K144 & S32K146运算速度

[zhengjianfei1]

Hi community，   

   最近发现一个比较奇怪的问题:S32K142运算速度比S32K144和S32K146慢。同样主频配置条件下，运行同样的代码，S32K142速度会慢一些。测试代码如下。测试结果是S32K142执行时间3.78ms，S32K144和S32K146执行时间是3.55ms。从芯片上看，都是M4内核，主频也设置来一样的，应该运行速度一样才对的，为什么会出现这样的差异的？

[Robin_Shen]

Hi jianfei,

是否使用CLKOUT功能引出内部HCLK或者BUS_CLK，使用示波器观察其频率是否一致？

如果使用IO口反转方式来测代码执行时间其实是不准确的，因为从MCU执行反转IO代码到实际IO口反转电平还需要一段时间。（当然对你这个测试目的来说是没有问题的，因为如果频率配置相同IO口翻转消耗的时间应该也是相同的）

这篇文章Cycle Counting on ARM Cortex-M with DWT提到的DWT模块可以用来测代码执行时间。（你也可以使用SysTick观察test函数前后的counter差值）

Best Regards,

Robin

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[zhengjianfei1]

Hi Robin，

      按照您的方法测试，CLOCK OUT将bus CLK输出，S32K142和S32K146的结果是：S32K142 23.99MHZ，S32K146 23.98MHZ，两者几乎无差异。

     此外，代码里面增加SYSTICK部分代码，通过寄存器查看每次执行后SYSTICK的差值，代码如下。

测试情况是：S32K142执行test函数SYSTICK差值为：90475。S32K146执行test函数的SYSTICK差值为85388。可以看出，S32K146确实是比S32K142快一些，不知道为什么？

[Robin_Shen]

抱歉让你久等了，我刚得到AE的答复：

Please double check and confirm the S32K142 and S32K144/6 project using the same C compiler optimization level setting. You can find the detailed compilation configurations for a certain C file from its .arg file located in the same location under the project build target folder(here is Debug_FLASH, which is generated after build the project) as below for example:

In general, -o1 runs faster than -o0 due to less instructions generated for the same function in C code.

Tips: the S32DS example project is default set to -o1 optimization level, while a new created project has -o0 optimization level

Best Regards,

Robin

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[zhengjianfei1]

Hi Robin,

      我这边是新建的工程，确认了是没有开优化的，O0等级。如下。

[zhengjianfei1]

对了，还有一个信息。当我开启了指令缓存后，S32K142和S32K144两者速度就一样了，从SYSTICK差值可以看出，完全是一样的。从示波器的测试结果也一样的。我觉得会不会是S32K142和S32K144的flash读取速率有差异呢？

[Robin_Shen · Accepted solution]

Hi jianfei,

Yes, you are right, this can be caused by the P-Flash port width difference between S32K142 and S32K144:

36.1.2 Flash memory sizes

S32K144 has two 256KB P-Flash interleave block and form a 128-bit port width for data access. while S32K142 has a non-interleave 256KB P-Flash block and its access port width is 64-bit. This feature is very useful for Instruction and Data Speculation & Prefech implemented on S32K1xx Flash controller(detailed configurations can be refered to OCMDR0~OCMDR2 register of MSCM module), and it is enabled by default.

34.4.2.18 On-Chip Memory Descriptor Register (OCMDR0).png

Best Regards,

Robin

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