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iMX RT1062 Qtimer configuration

Question asked by Andre marcus on Mar 30, 2020
Latest reply on Apr 29, 2020 by Kerry Zhou

I have two GPIOs that I configured as Qtimers so that I can generated a PWM with different duty cycles per channel: 

IOMUXC_SetPinMux(
       IOMUXC_GPIO_B0_00_QTIMER1_TIMER0,       /* GPIO_B0_00 is configured as QTIMER1_TIMER0 */
       0U);                                    /* Software Input On Field: Input Path is determined by functionality */
   IOMUXC_SetPinMux(
       IOMUXC_GPIO_B0_01_QTIMER1_TIMER1,       /* GPIO_B0_01 is configured as QTIMER1_TIMER1 */
       0U);                                    /* Software Input On Field: Input Path is determined by functionality */

 

I found out that the configurations of these channels conflict, see below. Can anyone tells me how this should be configured? how can I configure cmpld1/2 for both GPIO pins ( TMR1 channel 0 and TMR1 channel1) so that they don't conflict?

 

#define QTMR_EDMA_REQUEST_CMPLD2_SOURCE    kDmaRequestMuxQTIMER1Cmpld1Timer0Cmpld2Timer1
#define QTMR_EDMA_REQUEST_CMPLD1_SOURCE    kDmaRequestMuxQTIMER1Cmpld1Timer1Cmpld2Timer0
#define QTMR_EDMA_REQUEST_LD2CMPLD1_SOURCE kDmaRequestMuxQTIMER1Cmpld1Timer0Cmpld2Timer1
#define QTMR_EDMA_REQUEST_LD2CMPLD2_SOURCE   kDmaRequestMuxQTIMER1Cmpld1Timer1Cmpld2Timer0

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