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Having trouble with ADC clock configuration

Question asked by sparkee on Mar 2, 2020
Latest reply on Mar 25, 2020 by sparkee

Using FreeMASTER, I'm able to get around 1.1ms reads from my ADC.  I would like to be reading .1ms or even .01ms but I'm not having any luck.  I'm pretty sure it's an issue with my model and not a FreeMASTER limitation because I've seen other forum posts that look like faster reads are happening.

 

For reference:

I started with the adc_pdb_trigger_s32k14x example model

I'm running a fixed step size of .0001 at 80MHz system clock using the S32K144EVB.  I'm using prescaler value of 2 in the PDB_Config block so (I believe) I'm operating the ADC clock at 40MHz. 

 

It should be noted that using fixed step size of .001 and .0001 makes no discernible difference to my ADC read.  Changing from .001 to .01 changed my ADC read from 1ms to 10ms, as expected.

 

I'm struggling with clocking though so I'm pretty sure that's where the problem is.  According to the data sheet, fadck has a max of 50MHz to operate reliably.  I assume this means I need to scale the 80MHz down to 40MHz but is the PDB_Config the correct place?  According to the help documentation, this prescaler is dividing the peripheral clock (BUS_CLK), not the system clock. I don't know where else I can divide the system clock.  I'm having trouble following the clocking diagram in the ref manual but it looks like I would divide the system clock in the DIVBUS block.  Not sure how to do that with the Simulink Toolbox.  The only place I see for clock division is PDB_Config.

 

 

 

I'm seeing ADC using the BUS_CLK as peripheral clock but Note1 below says not to misinterpret the interface clock as BUS_CLK.  I have no idea what that means:

 

 

 

When I look at this section of ref manual, I'm further confused.  My only two options for clock speed are 112 and 80.  Those are both acceptable for HSRUN but only 80 is acceptable for RUN.  Does this mean I'm always using HSRUN or am I switching between HSRUN and RUN by switching from 112 to 80?  How does this affect SYS_CLK/BUS_CLK?

 

 

I've read through multiple forum posts and a large amount of documentation and I don't feel anything about ADC clocking is obvious with the Toolbox but other people seem to be successful with it so I'm either missing something or I'm just not as smart as I think I am!  Using this post I was able to understand how and why the PDB works but it's not mentioned how he got his 8000 modulus.  I assume he got it by dividing his step size of .0001 by the period of 80MHz (125n).  That gives 8000.  Not sure why he's using 80MHz though. At any rate, I've tried to replicate his .0001 readings using his settings and I'm unable to do it.  No matter what I change, I always get around 1.1ms updates.  I'm attaching my model.  Any help would be appreciated.

 

Thank you

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