I would like to connect 8 1080p@10fps(24bpp max) cameras to iMX8QM. iMX8QM has 2 MIPI CSI2 ports, each capable of 1.5Gbps per lane. I would be using 4 virtual channels per MIPI CSI2 port. There are 8 ISI processing pipeline channels, that i can use to process these data. I would be able to configure a maximum of 2K line per ISI processing channel. So, I think, it is possible to capture and put into memory from 8 cameras at 1080p@10fps(24bpp max) simultaneously.
I came across below in Errata sheet, which I think applies to Silicon Revision iMX8QM B0 as below:
ERR050066: ISI: Data overflows occur when input streams exceed AXI transaction frequency
Workaround: "The design target was intended to support up to a single 8 Mpixel (4K) stream at 30 fps, or multiple streams up to the equivalent data rate."
My questions are as follows:
1. Why does this errata workaround say this "multiple streams up to the equivalent data rate of 4K stream" ? By theory, cannot the ISI processing pipeline(without this Errata, in theory) support processing of 16K(2K per pipeline per channel x 8 such pipeline channels) resolution at the same time ? Is it talking about only the sensor capture ? Even if it is sensor capturing, since there are 2 MIPI CSI2 port each capable of 1.5Gbps per lane(& 4 such lanes), would it not be maximum capture of 8K stream instead of 4K stream ? Or am I missing out something here ?
2. Is Errata ERR050066 addressed in C0 revision ? When would iMX8QM C0 Silicon revision release for purchase ?