8 x 1080p MIPI CSI2 cameras capture in iMX8QM

[dwarakeshradhak]

Hi,

I would like to connect 8 1080p@10fps(24bpp max) cameras to iMX8QM. iMX8QM has 2 MIPI CSI2 ports, each capable of 1.5Gbps per lane. I would be using 4 virtual channels per MIPI CSI2 port. There are 8 ISI processing pipeline channels, that i can use to process these data. I would be able to configure a maximum of 2K line per ISI processing channel. So, I think, it is possible to capture and put into memory from 8 cameras at 1080p@10fps(24bpp max) simultaneously. 

I came across below in Errata sheet, which I think applies to Silicon Revision iMX8QM B0 as below:

ERR050066: ISI: Data overflows occur when input streams exceed AXI transaction frequency 

Workaround: "The design target was intended to support up to a single 8 Mpixel (4K) stream at 30 fps, or multiple streams up to the equivalent data rate."

My questions are as follows:

1. Why does this errata workaround say this "multiple streams up to the equivalent data rate of 4K stream" ? By theory, cannot the ISI processing pipeline(without this Errata, in theory) support processing of 16K(2K per pipeline per channel x 8 such pipeline channels) resolution at the same time ? Is it talking about only the sensor capture ? Even if it is sensor capturing, since there are 2 MIPI CSI2 port each capable of 1.5Gbps per lane(& 4 such lanes), would it not be maximum capture of 8K stream instead of 4K stream  ? Or am I missing out something here ?

2. Is Errata ERR050066 addressed in  C0 revision ? When would iMX8QM C0 Silicon revision release for purchase ?

[igorpadykov]

Hi Dwarakesh

in general your considerations are correct.

>1. Why does this errata workaround say this "multiple streams up to the equivalent data rate of 4K stream"

errata is caused by performance limitation, so  "equivalent data rate of 4K stream" is validated

recommended performance.

> By theory, cannot the ISI processing pipeline(without this Errata, in theory) support processing

>of 16K(2K per pipeline per channel x 8 such pipeline channels) resolution at the same time ?

unfortunately there are no "theoretical" ISI performance characteristics, ISI is complex module and

it is not possible to calculate its performance using some formulas.

>Is it talking about only the sensor capture ? Even if it is sensor capturing, since there are 2 MIPI CSI2

>port each capable of 1.5Gbps per lane(& 4 such lanes), would it not be maximum capture of 8K

>stream instead of 4K stream  ? Or am I missing out something here ?

you are right, errata is applicable only to ISI processing capability. No limitation for storing data to memory.

>2. Is Errata ERR050066 addressed in  C0 revision ? When would iMX8QM C0 Silicon revision release for purchase

there is no "iMX8QM C0 Silicon revision", probably you confused with i.MX8QXP C0 revision.

i.MX8QM production parts are listed in Table 2. i.MX 8QuadMax Orderable part numbers

i.MX 8QuadPlus Automotive and Infotainment Applications Processors

Best regards
igor
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[dwarakeshradhak]

Hi Igor,

Thanks a lot for your quick reply.

>errata is caused by performance limitation, so  "equivalent data rate of 4K stream" is validated

>recommended performance.

The Errata states that "The design target was intended to support up to a single 8 Mpixel (4K) stream at 30 fps" but due to this Errata it can support an equivalent of "sensors which add up to less than 2Mpixel are supported with current design"

Because even if the Errata is addressed in next hardware silicon revision of iMX8QM, still my requirement of 8x1080p(making it 8K) is not supported by design since it says design target was intended to support 8 Mpixel (4K). Is this design statement correct or is it a typo, since I see it in both iMX8QXP and iMX8QM errata, the same value ? Since there are 2 MIPI CSI, each capable of 4K@30, shouldn't it be a maximum of 8K in the case of iMX8QM barring this errata. If not, what is the reason for this restriction of the design target of 4K @ 30 fps like any buffer limitations etc ?

>you are right, errata is applicable only to ISI processing capability. No limitation for storing data to memory.

Does this mean, if I just put the MIPI CSI2 data into memory directly(using 8 pipeline channels) from 2 CSI2 pixel source without any ISI processing like CSC, scaling etc, wouldn't this errata apply ?

>there is no "iMX8QM C0 Silicon revision", probably you confused with i.MX8QXP C0 revision.

>i.MX8QM production parts are listed in Table 2. i.MX 8QuadMax Orderable part numbers

Is there a roadmap for a new revision of iMX8QM silicon, which addresses this Errata ? I know for iMX8QXP, this errata is addressed in C0 revision, but unfortunately we cannot use iMX8QXP, since it has only 1 MIPI CSI2 port.

Thanks in advance

[igorpadykov]

Hi Dwarakesh

>Is this design statement correct or is it a typo, since I see it in both
>iMX8QXP and iMX8QM errata, the same value ?

yes description in The Errata  is correct

>Does this mean, if I just put the MIPI CSI2 data into memory directly(using

>8 pipeline channels) from 2 CSI2 pixel source without any ISI processing like CSC,

>scaling etc, wouldn't this errata apply ?

right.

>Is there a roadmap for a new revision of iMX8QM silicon, which addresses this Errata ?

please contact local nxp marketing office for info about new revisions roadmap.

Best regards
igor

[dwarakeshradhak]

Hi Igor,

Thanks once again for your quick reply.

>>Does this mean, if I just put the MIPI CSI2 data into memory directly(using

>>8 pipeline channels) from 2 CSI2 pixel source without any ISI processing like CSC,

>>scaling etc, wouldn't this errata apply ?

>right.

I went through this "ERR050066: ISI: Data overflows occur when input streams exceed AXI transaction
frequency" Errata again. It talks about AXI transactions, which is the bus access to write into output buffer(which is memory). Also went through "15.13.1.3.6 Output Buffer Management" section in reference manual. It points to I believe the same AXI transactions that Errata talks for writing into output Y U V buffers. Does this mean, irrespective of ISI processing like sclaing CSC, etc (whether in bypass or not), shouldn't this errata affect the memory operations ? In which case, this Errata should affect my usecase of storing 8K@10 fps resolution into memory ? Or am I missing something ?

>please contact local nxp marketing office for info about new revisions roadmap.

Ok, thanks.

Thanks in advance.

[igorpadykov]

>Does this mean, irrespective of ISI processing like sclaing CSC, etc

>(whether in bypass or not), shouldn't this errata affect the memory operations ? 

yes, errata will not affect storing data from csi to memory, not involving ISI.

Best regards
igor

[khaledbalbaa]

@igorpadykov 

I would like to add a question to this topic

As I understood, in case I am doing some processing on the data in the ISI (CSC, scaling, etc) so the Errata will be applicable

My question is:

1. What is the maximum data rate I can use to avoid this issue?

2. I found mentioned that I can use 1 sensor with 2MPixel or 2 sensor each 1MPixel (with a total of 2MPixel for the whole ISI), at what max FPS? With how much max bits per pixel? (8-bit, 10-bit)

Thanks in advance