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LPC55S69 : gpio interrupt capacity

Question asked by Eugene Hiihtaja on Nov 7, 2019
Latest reply on Nov 11, 2019 by Eugene Hiihtaja

Hi !

 

I have got the next limitation what I not understand quite well.

 

By using PINT peripherals I'm able to have only 8 individual pins what can generate individual type of interrupts, edges /levels and etc. ( patterns can be used instead of individual pins.)

 

And looks like PINT interrupts is not able to wakeup  Core0 from Sleep mode.

SDK examples show that pin for use in ACTIVE mode is initialized individually as well.

 

Secure PINT might serve 2 extra pins from GPIO0 port.

 

From other side GINT0 and GINT1 can serve almost all pins for wakeup MCU from Power-Down mode.

I'm not quite sure if the same pin can be included in both GINTx block for serve both edges.

 

I need to use 17 external individual pins what generate interrupts in ACTIVE, Sleep and Power_Down mode.

 

GINTx is able to wakeup MCU from PowerDown or Sleep mode and I can identify source of interrupt e,g pin number.

But not clear if I can detect both edges.

 

But if MCU in Active mode looks like GINT dosn't work any more and only PINT can be used and I can serve only 8 interrupt pins. Is this so ?

 

I no need individual interrupt handler but I need solution when both edges of 17 GPIOs ( they all on GPIO1 port ) will cause ISR in ACTIVE, Sleep and PowerDown mode.

 

Gould you give advice about possible solution.

 

Regards,

Eugene

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