ddr init hangs

[maikkannan]

We have a custom LS1043A based board with one DDR4 (MT40A256M16GE-083E). we are using raw timing parameters.
our board is hangs on DDR initialization. This is my raw timing parameters and my console log.

dimm_params_t ddr_raw_timing = {
.n_ranks = 1,
.rank_density = 536870912u,
.capacity = 536870912u,
.primary_sdram_width = 16,
.ec_sdram_width = 0,
.registered_dimm = 0,
.mirrored_dimm = 0,
.n_row_addr = 15,
.n_col_addr = 10,
.bank_addr_bits = 0,
.bank_group_bits = 1,
.edc_config = 0,
.burst_lengths_bitmask = 0x0c,

.tckmin_x_ps = 833,
.tckmax_ps = 1500,
.caslat_x = 0x000DFA00,
.taa_ps = 13750,
.trcd_ps = 13750,
.trp_ps = 13750,
.tras_ps = 32000,
.trc_ps = 45750,
.trfc1_ps = 260000,
.trfc2_ps = 160000,
.trfc4_ps = 110000,
.tfaw_ps = 30000,
.trrds_ps = 5300,
.trrdl_ps = 6400,
.tccdl_ps = 5000,
.refresh_rate_ps = 7800000,
.dq_mapping[0] = 0x0,
.dq_mapping[1] = 0x0,
.dq_mapping[2] = 0x0,
.dq_mapping[3] = 0x0,
.dq_mapping[4] = 0x0,
.dq_mapping[5] = 0x0,
.dq_mapping[6] = 0x0,
.dq_mapping[7] = 0x0,
.dq_mapping[8] = 0x0,
.dq_mapping[9] = 0x0,
.dq_mapping[10] = 0x0,
.dq_mapping[11] = 0x0,
.dq_mapping[12] = 0x0,
.dq_mapping[13] = 0x0,
.dq_mapping[14] = 0x0,
.dq_mapping[15] = 0x0,
.dq_mapping[16] = 0x0,
.dq_mapping[17] = 0x0,
.dq_mapping_ors = 0,
};

#ifdef CONFIG_SYS_FSL_DDR4
{1, 1666, 0, 12, 7, 0x07090800, 0x00000000,},
{1, 1900, 0, 12, 7, 0x07090800, 0x00000000,},
{1, 2200, 0, 12, 7, 0x07090800, 0x00000000,},
{2, 1666, 0, 12, 7, 0x07090800, 0x00000000,},
{2, 1900, 0, 12, 7, 0x07090800, 0x00000000,},
{2, 2200, 0, 12, 7, 0x07090800, 0x00000000,},
#endif

//my console log

U-Boot SPL 2017.07 (Oct 11 2019 - 16:26:30)
Initializing DDR....
starting at step 1 (STEP_GET_SPD)
Filling dimm parameters from board specific file
Computing lowest common DIMM parameters for memctl=0
lowest_common_spd_caslat is 0xb
Warning: not all DIMMs ECC capable, cant enable ECC
tCKmin_ps = 833
trcd_ps = 13750
trp_ps = 13750
tras_ps = 32000
trfc1_ps = 260000
trfc2_ps = 160000
trfc4_ps = 110000
trrds_ps = 5300
trrdl_ps = 6400
tccdl_ps = 5000
twr_ps = 15000
trc_ps = 45750
Reloading memory controller configuration options for memctl=0
mclk_ps = 1250 ps
WARNING: Calling __hwconfig without a buffer and before environment is ready
WARNING: Calling __hwconfig without a buffer and before environment is ready
WARNING: Calling __hwconfig without a buffer and before environment is ready
Found timing match: n_ranks 1, data rate 1666, rank_gb 0
0 of 1 controllers are interleaving.
Checking interleaving options completed
dbw_cap_adj[0]=0
ctrl 0 dimm 0 base 0x0
ctrl 0 total 0x20000000
Total mem by __step_assign_addresses is 0x20000000
Total mem 536870912 assigned
FSL Memory ctrl register computation
FSLDDR: cs[0]_bnds = 0x0000001f
FSLDDR: cs[0]_config = 0x80040312
FSLDDR: cs[0]_config_2 = 0x00000000
FSLDDR: cs[1]_bnds = 0x00000000
FSLDDR: cs[1]_config = 0x00000000
FSLDDR: cs[1]_config_2 = 0x00000000
FSLDDR: cs[2]_bnds = 0x00000000
FSLDDR: cs[2]_config = 0x00000000
FSLDDR: cs[2]_config_2 = 0x00000000
FSLDDR: cs[3]_bnds = 0x00000000
FSLDDR: cs[3]_config = 0x00000000
FSLDDR: cs[3]_config_2 = 0x00000000
FSLDDR: timing_cfg_0 = 0x91550018
FSLDDR: timing_cfg_3 = 0x010c1000
FSLDDR: timing_cfg_1 = 0xbab48c52
FSLDDR: timing_cfg_2 = 0x0048c118
FSLDDR: ddr_cdr1 = 0x80040000
FSLDDR: ddr_cdr2 = 0x0000a181
FSLDDR: ddr_sdram_cfg = 0xc50c0008
DDR: ddr_data_init = 0xdeadbeef
FSLDDR: ddr_sdram_cfg_2 = 0x00401100
FSLDDR: ddr_sdram_mode = 0x03010210
FSLDDR: ddr_sdram_mode_3 = 0x00010210
FSLDDR: ddr_sdram_mode_5 = 0x00010210
FSLDDR: ddr_sdram_mode_5 = 0x00010210
FSLDDR: ddr_sdram_mode_2 = 0x00000000
FSLDDR: ddr_sdram_mode_4 = 0x00000000
FSLDDR: ddr_sdram_mode_6 = 0x00000000
FSLDDR: ddr_sdram_mode_8 = 0x00000000
FSLDDR: ddr_sdram_mode_9) = 0x00000500
FSLDDR: ddr_sdram_mode_11 = 0x00000400
FSLDDR: ddr_sdram_mode_13 = 0x00000400
FSLDDR: ddr_sdram_mode_15 = 0x00000400
FSLDDR: ddr_sdram_mode_10) = 0x00000000
FSLDDR: ddr_sdram_mode_12 = 0x00000000
FSLDDR: ddr_sdram_mode_14 = 0x00000000
FSLDDR: ddr_sdram_mode_16 = 0x00000000
FSLDDR: ddr_sdram_interval = 0x18600618
FSLDDR: clk_cntl = 0x03000000
FSLDDR: timing_cfg_4 = 0x00000002
FSLDDR: timing_cfg_5 = 0x03401400
FSLDDR: ddr_sdram_cfg_3 = 0x00000000
FSLDDR: timing_cfg_6 = 0x00000000
FSLDDR: timing_cfg_7 = 0x13300000
FSLDDR: timing_cfg_8 = 0x01006600
FSLDDR: timing_cfg_9 = 0x00000000
FSLDDR: dq_map_0 = 0x00000000
FSLDDR: dq_map_1 = 0x00000000
FSLDDR: dq_map_2 = 0x00000000
FSLDDR: dq_map_3 = 0x00000000
FSLDDR: zq_cntl = 0x8a090705
FSLDDR: wrlvl_cntl = 0x8675f607
FSLDDR: wrlvl_cntl_2 = 0x07090800
FSLDDR: wrlvl_cntl_3 = 0x00000000
Programming controller 0
Write to debug_29 as 00700046
total 1 GB
Need to wait up to 64 * 10ms
total_memory by __fsl_ddr_sdram = 536870912

[yipingwang]

Hello p saravanan,

You could use QCVS DDRv tool to do validation and optimization.

Please refer to DDRv user manual https://www.nxp.com/docs/en/user-guide/QCVS_DDR_User_Guide.pdf.

You need to create a DDR QCVS project, if there is SPD on the target, please use read from SPD option, otherwise you need to configure DDR related configuration parameters in properties panel according to the DDR data sheet after create a default QCVS DDR project, then generate DDR controller initial configuration parameters and use DDRv tool to do further optimization and validation.

After validation, please click Project->Generate Processor Expert Code to get u-boot parameters in file uboot_ddr1.c.

Thanks,

Yiping