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Fixing 'base address switching Change Err' which occurs randomly

Question asked by Kaartic Sivaraam Sankaranarayan on May 6, 2019
Latest reply on Mar 11, 2020 by Michael Tang



We are trying to add support for a new MIPI camera in the NXP i.MX 8M. It is a YUV camera. We are using the L4.14.78_1.0.0_MX8MQ BSP. We are getting 'base address switching Change Err' randomly when trying to stream. We made sure that the sensor side configuration was correct by evaluating the settings and clocks on a different platform. The we tried changing the MIPI receiver clock in the platform side i.e., the 'assigned-clock-rates' property in the following device tree entry. The device tree file is 'fsl-imx8mq.dtsi'.

    mipi_csi_1: mipi_csi1@30a70000 {
        compatible = "fsl,mxc-mipi-csi2_yav";
        reg = <0x0 0x30a70000 0x0 0x1000>; /* MIPI CSI1 Controller base addr */
        interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&clk IMX8MQ_CLK_DUMMY>,
                <&clk IMX8MQ_CLK_CSI1_CORE>,
                <&clk IMX8MQ_CLK_CSI1_ESC>,
                <&clk IMX8MQ_CLK_CSI1_PHY_REF>;
        clock-names = "clk_apb", "clk_core", "clk_esc", "clk_pxl";
        assigned-clocks = <&clk IMX8MQ_CLK_CSI1_CORE>,
                  <&clk IMX8MQ_CLK_CSI1_PHY_REF>,
                  <&clk IMX8MQ_CLK_CSI1_ESC>;
        assigned-clock-rates = <133000000>, <100000000>, <66000000>;
        power-domains = <&mipi_csi1_pd>;
        csis-phy-reset = <&src 0x4c 7>;
        phy-gpr = <&gpr 0x88>;
        status = "disabled";

When changing the values to the following:

        assigned-clock-rates = <266000000>, <400000000>, <66000000>;

We are successfully able to stream all the resolutions at the expected frame rates. However, the camera doesn't work at random times and we get the 'base address switching Change Err' when it doesn't work. The only way to fix this issue is to reboot the board (once or sometimes multiple times). Then it would work normally and we get uninterrupted streaming as usual. This indicated that the values we've configured for the platform side clock might be the problem. We tried to fix this issue which occurs at random times by reducing the platform side clock and correspondingly the sensor's MIPI clock too. We decreased platform side clocks to the following value:

        assigned-clock-rates = <266000000>, <150000000>, <66000000>;

Now we are able to avoid the 'base address switching Change Err' issue that occurs at random times but couldn't achieve the expected frame rates as we have also reduced the sensor side MIPI clocks. It would we nice if someone could shed some light on how to correctly program the platform side clocks which seems to be the key to adding support for our camera? We believe that the sensor side configuration and clocks are correct as we have tested it in a different platform.

To summarize,


1. In what scenarios does one face the 'base address switching Change Err'?


2. How to correctly program the values for the 'assigned-clock-rates' property in the device tree for any MIPI CSI2 sensor?


3. Are we missing something here?


4. For previous generation processors i.e, i.MX6, there's a document which describes in detail on how to configure the host for different sensors. It would be great if such a document was made available for i.MX 8M as well.