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i.MX7 RMII 50MHz clock

Question asked by Jonah Petri on Apr 2, 2019
Latest reply on Apr 3, 2019 by Jonah Petri

Hello,

 

I have read many entries on this forum about enabling a 50 MHz clock for use with a RMII ethernet PHY.  I don't think I have anything special in my setup.

 

What I have noticed is that the clock is gated off at startup, and nothing ever enables it. This is on the rel_imx_4.9.88_2.0.0_ga kernel, plus the changes from toradex to set the enet1 ref clock output enable bit in the IOMUX GPR1.

 

After boot, communication via MDIO works, but the PHY doesn't see a link. Reading CCM_TARGET_ROOT78:

# devmem 0x3038A700
0x02000000

Note the enable bit (0x10000000) is off for ENET1_REF_CLK_ROOT.

If I turn it on:

# devmem 0x3038A700 32 0x12000000
fec 30be0000.ethernet eth0: Link is Up - 100Mbps/Full - flow control off
IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready

Everything is great.

 

So, what is supposed to be ungating that clock?  None of the devtree examples I have seen use it.

 

Any help would be appreciated!

 

Some reference links I have read:

RMII interface on the IMX7 

How to output 50MHz on a pin of imx7d constantly 

 

devtree is as follows:

&fec1 {
    pinctrl-names = "default";
    pinctrl-0 = <&pinctrl_enet1>;
    
    clocks = <&clks IMX7D_ENET1_IPG_ROOT_CLK>,
        <&clks IMX7D_ENET_AXI_ROOT_CLK>,
        <&clks IMX7D_ENET1_TIME_ROOT_CLK>,
        <&clks IMX7D_PLL_ENET_MAIN_50M_CLK>,
        <&clks IMX7D_ENET1_REF_ROOT_CLK>;
        
    clock-names = "ipg", "ahb", "ptp",
        "enet_clk_ref", "enet_out";

    assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
             <&clks IMX7D_ENET1_TIME_ROOT_CLK>;
    assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
    assigned-clock-rates = <0>, <100000000>;
    
    phy-mode = "rmii";
    phy-reset-gpios = <&gpio3 28 GPIO_ACTIVE_LOW>;
    fsl,magic-packet;

    status = "okay";
};

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