Could you please provide information about the MPC546R cores operation.
Hi, MPC57xx does not use LSM/DPM modes, but device has main core and checker core (so called Safety Lake) as you can see in the picture below. These can be enabled or disabled, thus the protection is available or not, but safety lakes cannot be used for increasing of device overall performance.
Main core and checker are almost the same, but differs in absence of some sub-blocks in its checker variant (caches, nexus). Its number is decreased by one (e200z720 -> e200z719). Safety core operates in delayed lockstep mode (LSM) to allow the highest safety level to be reached. The checker core will receive all inputs delayed by two clock cycles. Outputs of the checker core will be compared with outputs of the master core. Any differences will be flagged as an error and processed by the FCCU.
Hope it helps to understand the principle.
Thanks for quick update on Core operations. I am planning to run the two cores with deferent software's and I need to enable safety lake as well. So could you please provide sample code to run the two different SW on the two main cores and safety lake enable.
Such example you may find for instance here:
Example MPC5746R DPM (multicore) GHS614
What's the difference telling whether safety lake is enabled or not is LOCKSTEP EN bit in the DCF_UTEST_Miscellaneous client. By default lockstep in enabled.
It means in the moment Main Core 0 is enabled, Checker Core 0s is enabled as well.
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