USB 3.0 Raw Throughput

[bharatkumarbach]

I loaded g_serial gadget driver to enumerate in device mode using

modprobe g_serial use_acm=0 idVendor=0xABCD idProduct=0xABCD

I wrote a console app in windows which uses WinUSB library to receive the data in a tight loop from the device(sending in a tight loop)

When connected with 2.0 cable I can see throughput as 45 MBps which is close to theoretical values.

But when connected with 3.0 cable throughput just reaches 80 MBps.

I need help knowing what's the bottleneck (g_serial or Windows Host)?

Since I have two iMX8M boards, I thought of eliminating windows and make one board act as host to other.

Yocto-Image used: core-image-base with libusb1 appended

wrote a console app (Host side) which uses LibUSB-1.0 library to receive the data in a tight loop from the device(sending in a tight loop).

When connected with 2.0 cable I can see throughput as just 6 Mbps and see following error continuously popping on the terminal.

"xhci-hcd xhci-hcd.0.auto: WARN Event TRB for slot 3 ep 2 with no TDs queued?0 > 0"

And when the error messages stop, I see throughput hit 45 MBps.

This repeats : Error messages for some time and stops and then start again.

Find the attachments for host-side and device-side code and block diagram of the setup.

Board: iMX8M

[igorpadykov]

Hi Bharat

seems processor arbiters NOC/NIC settings were not optimized for that module, also

one can test with unit tests:

043-Performance-Test.txt\doc\mxc_usb_test\test - imx-test - i.MX Driver Test Application Software 

Best regards
igor
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[bharatkumarbach]

Why do I have to care about NOC/NIC settings when USB ports are connected directly (no intentions to use g_ether).

The expected result of the performance test you suggested is 15 MBps. Already seeing 80 MBps, trying to achieve speeds around 3-4 Gbps

[igorpadykov]

suggestion was to use mass storage test with "dd", not g_ether.

NOC/NIC settings defines how data from usb module passes through processor buses.

For example below i.MX6Q NIC-301 Bus System, i.MX8M has much complex diagram

~igor

[amuresan]

Hi,

    Respectfully, you are not giving precise answers.

NOC/NIC settings defines how data from usb module passes through processor buses

(1) Which settings?

Furthermore, you linked to unit tests with expected results of 15MB/sec; why?

My colleague has achieved 

80 MBps, 

so how is 15MB/sec relevant to him?

He is trying to achieve speeds around 3-4 Gbps

Furthermore, why have you marked the question as "Assumed Answered"?

It is up to the poster to mark it as answered.

Please change it back to "Unanswered" and let the poster tell you when he thinks the question is answered.

[amuresan]

Thank you for that download.

The way I understand the phrase “bus arbiter” is that arbitration has to occur between peripherals for access to send data to/from the ARM core. 

If the only peripheral active is USB, then USB is not competing with any other peripheral for bus access so arbitration is not an issue. 

Therefore, why are the bus arbiter settings relevant in this discussion of USB 3.0 throughput?

Where is the competition for bus access happening?

[igorpadykov]

>phrase “bus arbiter” is that arbitration has to occur between peripherals for access to send data to/from the ARM

not sorry. Not only to/from the ARM.

Between any peripherals.

Best regards
igor

[igorpadykov]

> arbitration has to occur between peripherals for access to send data to/from the ARM core. 

not sorry. Data from/to usb module passes to memory also through bus arbiters

>Where is the competition for bus access happening?

arbiters can be configured for different policies, so that one bus master does not hold

whole bus, leaving some predefined bandwidth for other masters (even they are not working at all).

Just for reference one can look at arm NIC301 documentation

https://static.docs.arm.com/ddi0397/g/DDI0397G_amba_network_interconnect_nic301_r2p1_trm.pdf 

Most full description how bus arbiters work is provided in Chapter 45 Network Interconnect Bus System (NIC-301)

i.MX6DQ Reference Manual

http://www.nxp.com/docs/en/reference-manual/IMX6DQRM.pdf

i.MX8M has similar bus arbitration scheme, but more complicated.

Best regards
igor

[amuresan]

We need to understand the USB 3.0 capabilities of this processor. 

Can you provide a flash image and source code that is optimized for maximum usb 3.0 throughput?

Even if all other peripherals have to be turned off, we would still find this sample flash image very useful as it would give us a ceiling for usb 3.0 

[Yuri]

Hello,

  the following may be useful.

https://community.nxp.com/message/1092076 

Regards,

Yuri.

[bharatkumarbach]

I have performed the tests recommended by igorpadykov‌ and seen the read throughput from 150-170 MBps.

Note: No bottleneck from the hard drive I used as it can do 400+ MBps

Now I am truly interested to know the internal characterization USB speeds at NXP.

YuriMuhin_ng‌ : USB 3.0 performance on iMX8M  gives me no answer except that we have to propose NXP professional services to achieve more speeds than 170 MBps. 

Thanks and Regards,

Bharat

[igorpadykov]

>Can you provide a flash image and source code that is optimized for maximum usb 3.0 throughput?

sorry such image is not available. One can try to test this on i.MX8M EVK NXP reference board

with Linux Binary Demo Files - i.MX 8MQuad EVK

https://www.nxp.com/webapp/Download?colCode=L4.9.88_2.0.0_MX8MQ&appType=license&location=null 

Best regards
igor