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[S32K146] : Need help about ADC management

Question asked by Sebastien Le Diouris on Nov 12, 2018
Latest reply on Nov 12, 2018 by Daniel Martynek

Hello wonderful community,


I am working on S32K146 µc, and I try to "play" with ADC functionnality, but I occurs any understanding.

It is about SC1 (ADC Status and Control Register 1) and RA (ADC Data Result Registers).

These registers have each one 16 possible addresses. So I think basically than each address is for each ADC, I mean for ADC0 --> SC1[0] and RA[0], ADC1 --> SC1[1] and RA[1], ADC2 --> SC1[2] and RA[2], ..., ADC15 --> SC1[15] and RA[15]

But it seems unexact because ADCH from SC1 defines the channel used.

So I am a little lost, someone can help me to understand please.


Thanks by advance