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could MPC5746C slave DSPI2 correct clock/bit skew error on next comming CS period

Question asked by wesley xie on Oct 25, 2018
Latest reply on Nov 2, 2018 by wesley xie

Hi, NXP guys

Kirk HumphriesMandar JoshiDhaval ShahRHinnenJames TrudeauMartin Wennerstromvcentea1 vcentea1Marc PaquetteRuth HendrixAlban Rampon

on our board design, the MPC5746C play as a SPI slave (DSPI2), and the SPI master is IMX6.d.

I am wondering if a clock/bit skew error occured in one CS period on the SPI bus (which may caused by electronic jamming or Master start sending data before Slave ready ), will this error still exist in the next CS period ?

 

I understand the Rx / Tx datas on the MPC5746C(slave) side will goes wrong if clock/bit skew occured in current CS period,

but can the MPC5746C Rx / Tx correct datas on the next comming CS (CS deasserted and then asserted) without  Application software doing anything ?

 

if yes, could you please explain how it works ?

if not, could you please teach me how to fix this issue ?

 

thanks and best regards.

 

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