[i.MX6 ULL] External impedance of signals connected to the ADC

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[i.MX6 ULL] External impedance of signals connected to the ADC

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ceggers
Contributor V

IMX6ULLIEC.pdf, page 98

Characteristic ConditionsSymb Min TypMaxUnitComment
Analog Source Resistance

12 bit mode f ADCK =

40MHz ADLSMP=0,
ADSTS=10, ADHSC=1

RAS1kohmsTsamp=150ns

RAS depends on Sample Time Setting (ADLSMP, ADSTS) and ADC Power Mode (ADHSC, ADLPC). See charts for Minimum Sample Time vs RAS.

Where can I find these "charts" with RAS vs. minimum sample time? What is the largest RAS value which the ADC can handle (at the lowest possible sampling time)?

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gusarambula
NXP TechSupport
NXP TechSupport

Hello Christian Eggers,

You can refer to the charts on Section 4.13.1.1.1 of the i.MX6SX datasheet (link below) as the ADC module is like that of the i.MX6ULL.

https://www.nxp.com/docs/en/data-sheet/IMX6ULCEC.pdf

Also refer section 14.5.1.1 of the i.MX6SX Reference manual for proper conversion.

https://www.nxp.com/docs/en/reference-manual/IMX6SXRM.pdf

I hope this helps!

Regards,

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626 Views
gusarambula
NXP TechSupport
NXP TechSupport

Hello Christian Eggers,

You can refer to the charts on Section 4.13.1.1.1 of the i.MX6SX datasheet (link below) as the ADC module is like that of the i.MX6ULL.

https://www.nxp.com/docs/en/data-sheet/IMX6ULCEC.pdf

Also refer section 14.5.1.1 of the i.MX6SX Reference manual for proper conversion.

https://www.nxp.com/docs/en/reference-manual/IMX6SXRM.pdf

I hope this helps!

Regards,