AnsweredAssumed Answered

IMXRT1050 SEMC SRAM 16-bit Write

Question asked by Viktor Nagy on Jul 26, 2018
Latest reply on Sep 14, 2018 by Viktor Nagy



We made a control circuit with an MIMXRT1052DVL6B and an (Intel) FPGA.
The IMXRT1050 and the FPGA are connected together with the 16-bit external memory interface (SEMC).
The 16 bit AXI memory reads work as expected, for every same address reads we see a single, separate transaction on the parallel bus.
By the 16 bit (aligned) AXI memory writes however we see always four 16-bit write transactions at consecutive addresses.
Here is the code snippet for the test:
int cnt = 0;
volatile uint16_t * fp3 = (volatile uint16_t *)0x80000008;
volatile uint16_t * fp4 = (volatile uint16_t *)0x8000000A;
*fp4 = cnt++;
uint16_t v2 = *fp4;
*fp3 = cnt++;
uint16_t v1 = *fp3;
uint16_t v3 = *fp3;


In the attachment there is an oscilloscope recording of the SEMC control signals for this test.

Ray description:

  ray 1: SEMC CS6# (SRAM Chip select)
  ray 2: SEMC OE#
  ray 3: SEMC WE#
  (The SEMC ADV# is not displayed, but we use 16 bit Address / Data multiplexing)
By the FPGA the adjacent registers can not be filled with any random content, and I suspect it would cause a problem also by simple SRAM devices (beside the performance degradation).
Reading more times the reference manual we did not find a solution for this problem.
The only workaround we found is to do the writes with IP-Commands which is much slower.
Can you confirm this behaviour?
Or is there settings for the IMXRT1050 to disable this always 64-bit burst write mode for the AXI writes at the SEMC?
If you need more information please just ask.