I am still having the same issue can you please help me fix this .I just want to read the gpio ports and these are the spi transactions i send
Hi,
The usual steps on the master side for writing are:
* Configure desired speed within slave spec
* Assert SS/CS
* Send write command
* Start sending data/Ignore incoming data
* Stop by de-asserting SS/CS
The usual steps on the master side for reading are:
* Configure desired speed within slave spec
* Assert SS/CS
* Send read command
* Send dummy data/received data
* Stop by de-asserting SS/CS
In the image you sent I cannot see the SS/CS configuration unless is the “SPI EN” signal in which case is not doing what it supposed to do.
Regards,
Jose
NXP Semiconductor
i still have the same problem.you can see my spi enable line goes low during the transaction .but my miso line returns ff.
I write to reg A abd read on reg B.