I am Using Keil as S32K IDE,Now I have a problem .EveryTime I want to execute
It will Enter HardFault,I don't know why,because in S32 DS ,The same code works well,Can anybody help me to solve this issue? Thanks.
I got no the solution for your case but I got a way to investigate about the reason of that fault (I'm trying to resolve a similar issue on a project based a IAR tool chain).
Put a break point into the Hard fault handler position (in the ICF file that point is positioned in the start driver "startup_S32K144.s".
When the failure happen the execution should stop there.
Then check HFSR = HardFault Status Register, which should contain the information about what caused the HardFault handler activation.
There are different reasons according to the bit assignments:
b31 - DEBUGEVT: Reserved for debug reasons.
b30 - FORCED: Check the other fault status registers (I think is intended to check the CFSR)
b02 - VECTTBL: All other bits are reserved.
For forther informations you can check the links below:
HardFault Status Register
Configurable Fault Status Register
Let me know if you find a way to get through this because I'm stuck as well.
You may refer also to
Fault handling on S32K144
I dont use Keil, nor IAR.
Keil has a similar appnote on fault exceptions:
Keil Tech Support recommends increasing the Stack and Heap values in startup_xyx.s
They assume your program is running OK until you add this line.
It looks to me that the interrupt vector is placed in FLASH.
In order to use InstallHandler function the interrupt vector must be placed in RAM.
I currently do not have the linker file for KEIL, but there should be a symbol to place the interrupt vector table in RAM.
The Linker file I was working with was the one provided in the SDK for the S32K IDE (S32ds with IAR tool chain): S32K144_64_flash.icf which differs from S32K144_64_ram.icf right in the vector table which is defined in RAM (S32K144_64_ram.icf is provided in the same SDK's example).In both cases I have the same problem.I believe that I don't even reach the handler installation because the Hard failure is risen up after the 1st attempt to set up the configuration for the Fault Mode Status (FMS) register of the FTM0.
Below the sequence visualized:
Here's the start up take place:
Then, after the main invocation, there is the initialization of the FTM0 unit...
Inside that function there is a so called "FTM_DRV_Reset" which try the 1st access to the timer...
Inside the very 1st WR operation is a reset of the FMS:
That operation triggers the exception...
According to HFSR is a forced exception, so I checked CFSR = 0x00008200,
The last access was at 0x40038074 (address of "FTM0_FMS").
Using of the wrong linker file is not good. So thanks for the hint...That mistake in any case would be another problem to be fixed for sure.
It looks like the clock for the FTM instance is not enabled in PCC. This is why it goes to HardFault on the first register access.
Please use clock manager to enable the clock for FTM instance.
Thanks you a lot mate!!!
That was the right solution!.
Hi, The FTM needs the clock settings indeed.
If no set, the initial phase will lead to DefaultISR.
Retrieving data ...