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LS1021a FTM Quadrature Decoder Filtering

Question asked by Martin Hundebøll on Jan 11, 2018
Latest reply on Nov 19, 2018 by Deepak Kukreja

We have implemented a Linux driver for the FTM Quadrature Decoder on an LS1021a based platform. The decoder works, but we are unable to enable the channel filtering for PHA and PHB. Our setup consists of the following register writes:

 

/* working setup without filtering */
ftm_write(ftm_base, FTM_MODE, FTM_MODE_WPDIS | /* disable write protect */
                              FTM_MODE_FTMEN); /* enable FTM */
ftm_write(ftm_base, FTM_CNTIN, 0x0);           /* zero init value */
ftm_write(ftm_base, FTM_MOD, 0xffff);          /* max overflow value */
ftm_write(ftm_base, FTM_CNT, 0x0);             /* set counter value */
ftm_write(ftm_base, FTM_SC, FTM_SC_PS_1);      /* prescale with x1 */
ftm_write(ftm_base, FTM_QDCTRL, FTM_QDCTRL_QUADEN); /* select quad mode */
ftm_write(ftm_base, FTM_MODE, FTM_MODE_FTMEN); /* enable FTM (enable WP) */

According to the reference manual, filtering is enabled by configuring the filter values in FTM_FILTER, and set the two enable bits in FTM_QDCTRL:

 

/* Filter enable bits in FTM_QDCTRL aren't updated */
ftm_write(ftm_base, FTM_MODE, FTM_MODE_WPDIS | /* disable write protect */
                              FTM_MODE_FTMEN); /* enable FTM */
ftm_write(ftm_base, FTM_CNTIN, 0x0);           /* zero init value */
ftm_write(ftm_base, FTM_MOD, 0xffff);          /* max overflow value */
ftm_write(ftm_base, FTM_CNT, 0x0);             /* set counter value */
ftm_write(ftm_base, FTM_SC, FTM_SC_PS_1);      /* prescale with x1 */
ftm_write(ftm_base, FTM_FILTER, 0xff);         /* max filter on PHA and PHB */

/* this write seems to have no effect on the two filter bits? */
ftm_write(ftm_base, FTM_QDCTRL, FTM_QDCTRL_QUADEN |    /* select quad mode */
                                FTM_QDCTRL_PHAFLTREN | /* enable PHA filter */
                                FTM_QDCTRL_PHBFLTREN); /* enable PHB filter */

ftm_write(ftm_base, FTM_MODE, FTM_MODE_FTMEN); /* enable FTM (enable WP) */

When reading back the FTM_QDCTRL register only bit zero is set (FTM_QDCTRL_QUADEN), and the rest is zero. We have tried setting other bits in the same register (i.e. FTM_QDCTRL_PHAPOL and FTM_QDCTRL_PHBPOL), which works fine.

 

I have tried initializing the same registers on the LS1021a-twr evaluation board running the freescale BSP with the same results.

 

Is there some inter-register dependency for PHAFLTREN and PHAFLTREN that we have missed?

 

Thanks,

Martin

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