AnsweredAssumed Answered


Question asked by Andy Jones on Oct 31, 2017
Latest reply on Nov 2, 2017 by Andy Jones

Sometimes, at the "end" of a long 16-bit SPI frame transfer, the P1011 (SPI Master) shows RXCNT = 32, TXCNT = 30, and DON =0.  I suspect the full RX buffer encountered during the transfer has caused the SPI Master to suspended the transfer of the last character, but cannot find this behaviour detailed anywhere. 


I understand that the application SW has made an assumption that if the TXCNT indicates so many bytes have been sent from the TX Buffer, then a corresponding number of bytes will have been received into the RX Buffer (and attempts to read that many bytes out of the RX FIFO without checking RXCNT), but I wonder if propagation through TX and RX shift registers upsets that assumption.

A colleague wonders if the discrepancy has instead come about though the TX side not always keeping the TX FIFO adequately filled, so that at some point, transmission continued without valid data to send.  Would that happen, or would the SPI CLK pause when the buffer is empty but the full frame has not yet been sent?


Is there a more detailed description of P1011/P1020 SPI operation that you could direct me to?