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Where is MR3/ZQ calibration set up for mx6sl in u-boot or kernel?

Question asked by jayakumar2 on Oct 12, 2017
Latest reply on Oct 15, 2017 by igorpadykov


This is related to the previous post I made about ZQPAD and ZQ resistor values. Selecting ZQPAD and ZQ resistor value for i.mx6SL and LPDDR2 


We're using a custom board with i.mx6sl ( MCIMX6L8DVN10AB ) and EDB8132B4PM-1D-F-D LPDDR2 memory. I found that by changing drive strength settings in GRP_B0DS and others, I'm able to make boards that were previously failing, now pass. However, I still see upper addresses failing. I'm suspicious whether ZQ calibration is being run and also whether the MR3 setting is done for both chipselects on the LPDDR2 memory.


I am wondering where is ZQ calibration done and where does the MR3 register get set (for setting resistance of LPDDR2 DQ driver)? ie: which code function does it.


I found some code in arch/arm/cpu/armv7/mx6/ddr.c :


/* Step 7: Enable MMDC with desired chip select */
mmdc0->mdctl |= (1 << 31) | /* SDE_0 for CS0 */
((sysinfo->ncs == 2) ? 1 : 0) << 30; /* SDE_1 for CS1 */

/* Step 8: Write Mode Registers to Init LPDDR2 devices */
for (cs = 0; cs < sysinfo->ncs; cs++) {
/* MR63: reset */
mmdc0->mdscr = MR(63, 0, 3, cs);
/* MR10: calibration,
* 0xff is calibration command after intilization.
val = 0xA | (0xff << 8);
mmdc0->mdscr = MR(val, 0, 3, cs);
/* MR1 */
val = 0x1 | (0x82 << 8);
mmdc0->mdscr = MR(val, 0, 3, cs);
/* MR2 */
val = 0x2 | (0x04 << 8);
mmdc0->mdscr = MR(val, 0, 3, cs);
/* MR3 */
val = 0x3 | (0x02 << 8);
mmdc0->mdscr = MR(val, 0, 3, cs);


but I now believe that code does not get run. Even if u-boot is setup for SPL, it does not seem to be sufficient to set CONFIG_SPL=y as that code still does not seem to get reached.


Do you know where ZQ calib and MR3 is done for u-boot on 6sl? Should it be done in u-boot? Or is it in kernel and if it is done in kernel on 6sl, where is it being done? It seems critical to memory stability but not well documented.