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ls1021aqds  uboot nand boot

Question asked by shunping lin on Oct 12, 2017
Latest reply on Nov 9, 2017 by shunping lin

ls1021aqds NAND boot, firstly copy 8KB from NAND flash to IFC SRAM, then CPU execute in this SRAM.

 

I compiled the uboot and the size of uboot is > 8KB

-rw-rw-r-- 1 splin splin 35436 10月 12 14:31 u-boot-spl.pbl

 

So I think uboot must copy this code to SDRAM and change to execute in the SDRAM,

but I can't find the code in ls1021aqds.c . why?

 

I confused that the board_init_f() in ls1021aqds.c directly call board_init_r(NULL, 0).

the ls1021aqds board don't have enough space in IFC SRAM.

 

does anyone know the reson?? ?  Thanks!

 

 

 

 

 

 

 

 

The following is board_init_f(),which is called by ENTRY(_main) of crt0.S

#ifdef CONFIG_SPL_BUILD
void board_init_f(ulong dummy)
{
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
unsigned int major;

#ifdef CONFIG_NAND_BOOT
struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
u32 porsr1, pinctl;

/*
* There is LS1 SoC issue where NOR, FPGA are inaccessible during
* NAND boot because IFC signals > IFC_AD7 are not enabled.
* This workaround changes RCW source to make all signals enabled.
*/
porsr1 = in_be32(&gur->porsr1);
pinctl = ((porsr1 & ~(DCFG_CCSR_PORSR1_RCW_MASK)) |
DCFG_CCSR_PORSR1_RCW_SRC_I2C);
out_be32((unsigned int *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
pinctl);
#endif

/* Clear the BSS */
memset(__bss_start, 0, __bss_end - __bss_start);

#ifdef CONFIG_FSL_IFC
init_early_memctl_regs();
#endif

get_clocks();

#if defined(CONFIG_DEEP_SLEEP)
if (is_warm_boot())
fsl_dp_disable_console();
#endif

preloader_console_init();

#ifdef CONFIG_SPL_I2C_SUPPORT
i2c_init_all();
#endif

major = get_soc_major_rev();
if (major == SOC_MAJOR_VER_1_0)
out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);

dram_init();

/* Allow OCRAM access permission as R/W */
#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
enable_layerscape_ns_access();
#endif

board_init_r(NULL, 0);
}
#endif

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