AnsweredAssumed Answered

ICS trim reset during debug

Question asked by David Sherman on Jun 30, 2017
Latest reply on Jul 11, 2017 by Kerry Zhou

I've got a peculiar problem.  We are using a KE06Z128VLH4 and KDS 3.0.0.  The KE06 is using the FEI clock at 48 MHz and we are using a P&E Multilink Universal FX.  For some reason, during debug in one environment the ICS_C3 register which trims the internal clock is being reset to 0x80.  The default values are typically 0x4f-0x5b for the factory trim value.  What is strange is that using the same debug configuration settings and the same board, one computer is debugging normally with the ICS using the factory default trim, but on another the trim is being reset to 0x80, which is throwing the clock off.  We can't find any option under the debug settings to control this, and we are using the same ARP file.  We even tried deleting the debug configuration and creating a new one.  The board boots normally out of ROM and runs at the correct speed, it's just under debug on one machine the ICS is somehow being changed.  Is there some option that we are not finding?  I see the ARP file sets the ICS trim value, but is there someplace else the debugger changes it?  I've confirmed that the 0x3FE and 0x3FF locations contain 0x4F and 0x00 respectively for the board.