pge

LPC546xx SPIFI dual section XIP

Discussion created by pge on Jun 7, 2017
Latest reply on Jun 8, 2017 by jeremyzhou

Hello,

 

I plan to use a LPC546xx in a new design where I need an external Flash to store firmware.

I need two Flash section to be able to perform safe OTA firmware update in ping-pong mode. One section is updated while code is executed from the other section. 

 

Do you know if SPIFI can be used for such scenario ?

In the datasheet and user manual I can read :

SPIFI has two operational modes:

1. Memory Mode - whereby the contents of the FLASH are memory mapped in the chip.

2. Command Mode - whereby the user can manually construct command sequences for the flash.

SPIFI cannot switch over from Memory Mode to Command mode and vice versa without writing 1 to the RESET bit in the SPIFI Status Register and polling until it is cleared by hardware to ensure that the current mode has been aborted.

I understand that I cannot execute code from one section while updating another section. Is that correct ?

 

I also read :

The SPIFI on the LPC546xx has a reduced cache for accesses to the serial flash region of the memory map, so direct execution of code from external SPI flash memory is not recommended.

 

And somewhere else :

Provides XIP (execute in place) feature to execute code directly from serial flash.

Which statement is correct ?

 

Thanks in advance for any help

PGE

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