K22F DAC trigger documentation

[scottm]

I'm using the MK22FN1M0AVLH12 and the 12-bit DAC documentation seems to be a bit lacking.  The DAC chapter doesn't seem to have anything to say about hardware trigger sources, and the chip configuration section for the DAC doesn't even mention triggers at all.  The PDB section does show the DAC trigger.  Is that the extent of the documentation, or is there more somewhere?  The DAC block diagram looks like a joke, with the vague "other peripherals" block and "module signals".

I seem to have what I need for the moment.  I was trying to do a simple coherent write to the DAC register in an interrupt, and it was getting a lot of glitches.  The solution was to turn on the data buffer with the upper limit set to 0, trigger set to software mode, and then set the software trigger bit after writing to DACH and DACL.  To me, this is probably the simplest and most obvious mode you'd want to use the DAC in, yet the documentation doesn't seem to address it.

Thanks,

Scott

[xiangjun_rong]

Hi, Scott,

As you said that the RM of K22 is not clear about the DAC triggering source.

Firstly, the 12 bits DAC has software triggering mode and hardware triggering mode, for software tyyriggering mode, set the DACTRGSEL bit in DACx_C0 to select software triggering mode, it is okay to set the software trigger bit DACSWTRG after writing to DACH and DACL as you have done.

Fot hardware triggering mode, firstly clear DACTRGSEL to select hardwrae triggering mode. For hardware triggering mode, only PDB_CH2 can trigger DAC, if you want to trigger DAC with a fixed cycle time so that the DAC can output a waveform, I suggest you use PDB_CH2 to trigger DAC, firstly, configure PDB in software triggering mode by  set the TRGSEL=1111 in PDBx_SC, the cycle time of DAC is determined by PDBx_MOD register, then set the SWTRG in PDBx_SC, the PDB will count one by one. If you use  DAC0 module, you can clear EXT and set TOE bits in PDBx_DACINTCn, when the PDB counetr reaches the PDBx_DACINT0, the DAC0 will be triggered.

For detailed inf, pls refer to section 37.4.3 DAC interval trigger outputs

Hope it can help you

BR

Xiangjun Rong

[scottm]

Hi,

Thanks for the response.  I've got it working already, but my question is more about the organization of the documentation. The PDB section of the reference manual shows a block diagram with the DAC trigger connection, but one has to know to look in the PDB section first.  Nothing in the DAC sections makes any mention of the PDB and there's nothing to direct the reader there.

I have what I need, but it'd be nice to see this clarified in future versions of the manual.

Thanks,

Scott

[xiangjun_rong]

Hi, Scott,

I agree with you that the DAC triggering part in K22 RM is poor, I will contact documentation team so that they can modify the part.

Thank you for your understanding.

BR

Xiangjun Rong

[scottm]

Thanks.  I miss the older manuals (like for the HCS08 parts) where the peripheral chapters were all self-contained and had both the peripheral description and the chip-specific configuration, except for maybe the actual register addresses.  I understand the reasoning for the way it is now - it's easier to maintain a lot of manuals when you don't have to edit each chapter for every chip - but it also leaves the potential for a lot of gaps.

Regards,

Scott