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Obtaining advertised ECSPI timing on SS_B

Question asked by Jonah Petri on Mar 29, 2017
Latest reply on Apr 26, 2017 by Jonah Petri

Hello,

 

I'm using the i.MX7d with the linux 4.1.15 2.0.0 GA kernel, with a SPI peripheral connected to ECSPI3.  This is on the MX7D sabre board.  I need to have precise timing on the ECSPI transactions, and having read the reference manual and the datasheet it seems that it should be able to meet my needs.  However, I'm seeing unexpected results.

 

I need transactions (SS assertions) to occur at 1 MHz, and the SCLK to run at 16 MHz.  Burst width is set to 14 bits.  From the timing diagram in section 4.11.1.1 of the IMX7DCEC Electrical Characteristics document:

 

Given a SCLK at 16MHz, I would expect the CS4 time to be half a SCLK period as advertised, so CS4 should be approximately 32ns.  However, I see a much larger CS4 time: about 220ns:

 

 

What could be causing this discrepancy?  I am not using the PERIODREG register:

# devmem  0x3084001C
0x00000000

I set the ECSPI ipg and per clocks to 48 MHz:

# cat /sys/kernel/debug/clk/clk_summary | grep ecspi3
                      ecspi3_src           1            1   240000000          0 0  
                         ecspi3_cg           1            1   240000000          0 0  
                            ecspi3_pre_div           1            1   240000000          0 0  
                               ecspi3_post_div           1            1    48000000          0 0  
                                  ecspi3_root_clk           2            2    48000000          0 0  

Relevant ECSPI3 registers:

CONREG: 0x00D020F5

CONFIGREG: 0x00000100

 

How can I achieve the advertised timing on the SS_B pulse width?

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