Issues with PCIe initialization on i.MX7D Sabre Rev D

[annah]

Hi,

I am having issues with the PCIe interface on the i.MX7D Sabresd Rev D1 board. The PCIe interface is able to initialize when an Intel Wireless 5300 miniPCIe card is plugged in, however when an Intel Wireless 3160 is used both the device and the PCI bridge fail to initialize. I've verified the 3160 card's functionality with an i.MX6Q board, using the same kernel version (release 4.1.15_2.0.1), and this works fine. Do you know what is causing this issue?

Again, this was tested with:

• i.MX7D Sabre Rev D1
• BSP release L4.1.15_2.0.1

Output with 5300 connected:

root@imx7dsabresd:~# dmesg | grep -i pci
[ 0.250709] PCI: CLS 0 bytes, default 64
[ 1.087959] ehci-pci: EHCI PCI platform driver
[ 2.915297] 33800000.pcie supply pcie-bus not found, using dummy regulator
[ 2.984842] imx6q-pcie 33800000.pcie: PCI host bridge to bus 0000:00
[ 2.989929] pci_bus 0000:00: root bus resource [io 0x1000-0xffff]
[ 2.994815] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fefffff]
[ 3.000410] pci_bus 0000:00: root bus resource [bus 00-ff]
[ 3.004625] pci 0000:00:00.0: [16c3:abcd] type 01 class 0x060400
[ 3.004651] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x000fffff]
[ 3.004669] pci 0000:00:00.0: reg 0x38: [mem 0x00000000-0x0000ffff pref]
[ 3.004720] pci 0000:00:00.0: supports D1
[ 3.004728] pci 0000:00:00.0: PME# supported from D0 D1 D3hot D3cold
[ 3.004985] PCI: bus0: Fast back to back transfers disabled
[ 3.009470] pci 0000:01:00.0: [8086:4235] type 00 class 0x028000
[ 3.009545] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x00001fff 64bit]
[ 3.009817] pci 0000:01:00.0: PME# supported from D0 D3hot D3cold
[ 3.026197] PCI: bus1: Fast back to back transfers disabled
[ 3.030481] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
[ 3.030586] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x400fffff]
[ 3.036087] pci 0000:00:00.0: BAR 8: assigned [mem 0x40100000-0x401fffff]
[ 3.041602] pci 0000:00:00.0: BAR 6: assigned [mem 0x40200000-0x4020ffff pref]
[ 3.047547] pci 0000:01:00.0: BAR 0: assigned [mem 0x40100000-0x40101fff 64bit]
[ 3.053593] pci 0000:00:00.0: PCI bridge to [bus 01]
[ 3.057280] pci 0000:00:00.0: bridge window [mem 0x40100000-0x401fffff]
[ 3.063081] pcieport 0000:00:00.0: Signaling PME through PCIe PME interrupt
[ 3.068865] pci 0000:01:00.0: Signaling PME through PCIe PME interrupt
[ 3.074121] pcie_pme 0000:00:00.0:pcie01: service driver pcie_pme loaded
[ 3.074263] aer 0000:00:00.0:pcie02: service driver aer loaded
[ 7.594776] vgaarb: this pci device is not a vga device
[ 7.658858] vgaarb: this pci device is not a vga device

root@imx7dsabresd:~# lspci
00:00.0 PCI bridge: Synopsys, Inc. Device abcd (rev 01)
01:00.0 Network controller: Intel Corporation Ultimate N WiFi Link 5300

Output with 3160 connected:
root@imx7dsabresd:~# dmesg | grep -i pci
[ 0.250811] PCI: CLS 0 bytes, default 64
[ 1.087695] ehci-pci: EHCI PCI platform driver
[ 2.915456] 33800000.pcie supply pcie-bus not found, using dummy regulator
[ 3.178369] imx6q-pcie 33800000.pcie: phy link never came up
[ 3.182766] imx6q-pcie 33800000.pcie: failed to initialize host
[ 3.187543] imx6q-pcie: probe of 33800000.pcie failed with error -22

Thanks,

Anna

[Yuri]

Hello,

I hope the following helps.

Question, PCIe on i.MX7D SABRE cannot work 

Have a great day,

Yuri

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Note: If this post answers your question, please click the Correct Answer

button. Thank you!

[annah]

Hi Yuri,

Our hardware and software is configured as described in the forum post you linked and is functional with some devices, but the issue is that not all devices are able to initialize properly.

I found that modifying the pci-imx6.c driver so that the PCIe PHY is released from reset before the ~PERST signal to reset the PCIe device is toggled allowed both the 3160 card that was failing before to initialize properly.

I don't have access to the PCI SIG PCIe specifications documentation, would you or someone at NXP be able to confirm that the change I made is in accordance with the specifications? The i.MX7D TRM shows the start up sequence in Figure 11-56, however it doesn't include PERST. It does include a signal "CMN_RST", how is this signal controlled? I don't see it referenced in the driver.

Here are the changes I made in imx6_pcie_deassert_core_reset:

/* allow the clocks to stabilize */
udelay(200);

+    /*
+    * Release the PCIe PHY reset here for iMX7D
+    */
+    if (is_imx7d_pcie(imx6_pcie)) {
+       /* wait for more than 10us to release phy g_rst and btnrst */
+       udelay(10);
+       regmap_update_bits(imx6_pcie->reg_src, 0x2c, BIT(1), 0);
+       regmap_update_bits(imx6_pcie->reg_src, 0x2c, BIT(2), 0);
+       regmap_update_bits(imx6_pcie->reg_src, 0x2c, BIT(6), 0);
+
+       /* wait for phy pll to lock. */
+       pci_imx_phy_pll_locked(imx6_pcie);
+    }
+
   /* Some boards don't have PCIe reset GPIO. */
   if (gpio_is_valid(imx6_pcie->reset_gpio)) {
      gpio_set_value_cansleep(imx6_pcie->reset_gpio, 0);
      mdelay(20);
      gpio_set_value_cansleep(imx6_pcie->reset_gpio, 1);
      mdelay(20);
   }

   /*
-  * Release the PCIe PHY reset here
+ * Release the PCIe PHY reset here for i.MX6
   */
-    if (is_imx7d_pcie(imx6_pcie)) {
-       /* wait for more than 10us to release phy g_rst and btnrst */
-       udelay(10);
-       regmap_update_bits(imx6_pcie->reg_src, 0x2c, BIT(6), 0);
-       regmap_update_bits(imx6_pcie->reg_src, 0x2c, BIT(1), 0);
-       regmap_update_bits(imx6_pcie->reg_src, 0x2c, BIT(2), 0);
-
-       /* wait for phy pll lock firstly. */
-       pci_imx_phy_pll_locked(imx6_pcie);
-    } else if (is_imx6sx_pcie(imx6_pcie)) {
+    if (is_imx6sx_pcie(imx6_pcie)) {
         regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5,
         IMX6SX_GPR5_PCIE_BTNRST, 0);
      } else if (is_imx6qp_pcie(imx6_pcie)) {

Thanks,

Anna

[Yuri]

Hello, Anna !

  if possible, please create request regarding imx6_pcie_deassert_core_reset

in order to analyze it with app team.

Regards,

Yuri.