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PIT DMA trigger details

Question asked by Mark Butcher on Jan 10, 2017
Latest reply on Jan 11, 2017 by Bob Paddock

Hi All


I am trying to work out some details about the PIT's DMA trigger timing, specifically:
- can it be pending?
- can pending DMA be cleared to avoid unwanted triggering?


While working on timed DMA driven UART operation for DMX type applications, where accurate inter-character spacing can also be of importance for accurate timing, there is one behavior that is not defined exactly which I would like to fully understand.


Using a PIT timer as DMA trigger transmission characters are copied at an accurate periodic rate to the UART's data register (this works on LPUARTs but not on other types, but that is another topic which I will report on). The result is a stream of tx data with exact delays between each character - eg. in scope shot below. There is no CPU overhead since it is self-timed by the PIT for the programmed number of transfers.


There is a reference before the first character transmission at the time point when the PIT was started. Then the free-running PIT periodically triggers the next transfer with the same period..


However in some circumstances the behavior is not identical (the first time the PIT is used after a reset or after being used for other purposes). The timing can look like the second image below:


In this case the first DMA trigger fires immediately when the PIT is configured, rather than when it first times out. Once the PIT is free-running the inter-character spacing is as expected.


What is not clear is why the PIT generates a DMA trigger sometimes when configured/enabled and sometimes only when its fist times out. It is as if there is a DMA trigger 'pending' when enabled.


Does anyone have any knowledge about how this could be controlled (eg. by somehow clearing pending DMA triggers before the can fire)?






P.S. I put a reference binary at showing the behavior (on KL27 LPUART) as well as giving so additional information concerning the UART mode.