AnsweredAssumed Answered

T4240: Cannot change to alternative flash boot section

Question asked by Manuel Huber on Nov 4, 2016
Latest reply on Jun 13, 2017 by jakob danielsson



we have a T4240RDB board, on which we would like to update U-Boot. Currently there is a QorIQ SDK v1.5 U-Boot installed. We flashed a new SDK v2.0 U-Boot to the alternative boot section. When issued an "qix altbank" command to change to the altenative boot section command nothing happens (see log below). Changes to the board's SW3 DIP switch also has no effect. Always the SDK v1.5 U-Boot gets booted.


Has anyone an idea, how to change to the alternative U-Boot ?



U-Boot 2013.01QorIQ-SDK-V1.5 (Jan 17 2014 - 15:15:08)

CPU0:  T4240E, Version: 2.0, (0x82480020)
Core:  E6500, Version: 2.0, (0x80400120)
Clock Configuration:
       CPU0:1666.667 MHz, CPU1:1666.667 MHz, CPU2:1666.667 MHz, CPU3:1666.667 MHz,
       CPU4:1666.667 MHz, CPU5:1666.667 MHz, CPU6:1666.667 MHz, CPU7:1666.667 MHz,
       CPU8:1666.667 MHz, CPU9:1666.667 MHz, CPU10:1666.667 MHz, CPU11:1666.667 MHz,
       CCB:733.333 MHz,
       DDR:933.333 MHz (1866.667 MT/s data rate) (Asynchronous), IFC:183.333 MHz
       FMAN1: 733.333 MHz
       FMAN2: 733.333 MHz
       QMAN:  366.667 MHz
       PME:   533.333 MHz
L1:    D-cache 32 kB enabled
       I-cache 32 kB enabled
Reset Configuration Word (RCW):
       00000000: 16070019 18101916 00000000 00000000
       00000010: 70701050 00448c00 0c020000 f5000000
       00000020: 00000000 ee0000ee 00000000 000287fc
       00000030: 00000000 50000000 00000000 00000028
Board: T4240RDB, SERDES Reference Clocks: SERDES1=100MHz SERDES2=156.25MHz SERDES3=100MHz SERDES4=100MHz
I2C:   ready
SPI:   ready
DRAM:  Initializing....using SPD
Detected UDIMM 9JSF25672AZ-2G1K1
Detected UDIMM 9JSF25672AZ-2G1K1
Detected UDIMM 9JSF25672AZ-2G1K1
4 GiB left unmapped
    DDR: 6 GiB (DDR3, 64-bit, CL=13, ECC on)
       DDR Controller Interleaving Mode: 3-way 4KB
Flash: 128 MiB
L2:    2048 KB enabled
enable l2 for cluster 1 fec60000
enable l2 for cluster 2 feca0000
Corenet Platform Cache: 1536 KB enabled
Using SERDES1 Protocol: 28 (0x1c)
Using SERDES2 Protocol: 56 (0x38)
Using SERDES3 Protocol: 2 (0x2)
Using SERDES4 Protocol: 10 (0xa)
SRIO1: disabled
SRIO2: disabled
NAND:  2048 MiB
PCIe1: Root Complex, no link, regs @ 0xfe240000
PCIe1: Bus 00 - 00
PCIe2: disabled
PCIe3: Root Complex, no link, regs @ 0xfe260000
PCIe3: Bus 01 - 01
PCIe4: Root Complex, no link, regs @ 0xfe270000
PCIe4: Bus 02 - 02
In:    serial
Out:   serial
Err:   serial
Warning: SERDES2 expects reference clock 125MHz, but actual is 156.25MHz
Net:   Fman1: Uploading microcode version 106.4.10
Failed to connect
Failed to connect
cs4340_phy_init error.
cs4340_phy_init error.
Fman2: Uploading microcode version 106.4.10
cs4340_phy_init error.
cs4340_phy_init error.
Hit any key to stop autoboot:  0
=> qix altbank