AnsweredAssumed Answered

Flexbus and SDRAM Multiplex on K65F_169GBA

Question asked by Christie Su on Sep 14, 2016
Latest reply on Sep 19, 2016 by Hui_Ma


I am going to use 2 32-bit SDRAMs on SDRAM controller. And want to add 16-bit external flash to Flexbus.

Could anybody check if the following pin assignment should be OK if I don't want to use external multiplex circuit?


/* Initialize the SDRAMC pins */

/* Ungate the port clock */







/* CAS/RAS*/

PORT_SetPinMux(PORTB, 0UL, kPORT_MuxAlt5); // SDRAM_CAS_b

PORT_SetPinMux(PORTB, 1UL, kPORT_MuxAlt5); // SDRAM_RAS_b

/* WE */

PORT_SetPinMux(PORTB, 2UL, kPORT_MuxAlt5); // ENET0_1588_TMR0/SDRAM_WE

/* CS */

PORT_SetPinMux(PORTB, 3UL, kPORT_MuxAlt5); // ENET0_1588_TMR1/SDRAM_CS0

PORT_SetPinMux(PORTB, 4UL, kPORT_MuxAlt5); // ENET0_1588_TMR2/SDRAM_CS1

/* SDRAM Data*/

PORT_SetPinMux(PORTA, 24UL, kPORT_MuxAlt5); /* SDRAM_D15/FB_A15*/

PORT_SetPinMux(PORTA, 25UL, kPORT_MuxAlt5); /* SDRAM_D14/FB_A14*/

PORT_SetPinMux(PORTA, 26UL, kPORT_MuxAlt5); /* SDRAM_D13/FB_A13*/

PORT_SetPinMux(PORTA, 27UL, kPORT_MuxAlt5); /* SDRAM_D12/FB_A12*/

PORT_SetPinMux(PORTA, 30UL, kPORT_MuxAlt5); /* SDRAM_D11/FB_A11*/

PORT_SetPinMux(PORTA, 31UL, kPORT_MuxAlt5); /* SDRAM_D10/FB_A10*/

PORT_SetPinMux(PORTB, 6UL, kPORT_MuxAlt5); /* SDRAM_D23*/

PORT_SetPinMux(PORTB, 7UL, kPORT_MuxAlt5); /* SDRAM_D22*/

PORT_SetPinMux(PORTB, 8UL, kPORT_MuxAlt5); /* SDRAM_D21*/

PORT_SetPinMux(PORTB, 9UL, kPORT_MuxAlt5); /* SDRAM_D20*/

PORT_SetPinMux(PORTB, 10UL, kPORT_MuxAlt5); /* SDRAM_D19*/

PORT_SetPinMux(PORTB, 11UL, kPORT_MuxAlt5); /* SDRAM_D18*/

PORT_SetPinMux(PORTB, 12UL, kPORT_MuxAlt5); /* SDRAM_D9/FB_A9*/

PORT_SetPinMux(PORTB, 13UL, kPORT_MuxAlt5); /* SDRAM_D8/FB_A8*/

PORT_SetPinMux(PORTB, 14UL, kPORT_MuxAlt5); /* SDRAM_D7/FB_A7*/

PORT_SetPinMux(PORTB, 15UL, kPORT_MuxAlt5); /* SDRAM_D6/FB_A6*/

PORT_SetPinMux(PORTB, 16UL, kPORT_MuxAlt5); /* SDRAM_D17*/

PORT_SetPinMux(PORTB, 17UL, kPORT_MuxAlt5); /* SDRAM_D16*/

PORT_SetPinMux(PORTB, 20UL, kPORT_MuxAlt5); /* SDRAM_D31*/

PORT_SetPinMux(PORTB, 21UL, kPORT_MuxAlt5); /* SDRAM_D30*/

PORT_SetPinMux(PORTB, 22UL, kPORT_MuxAlt5); /* SDRAM_D29*/

PORT_SetPinMux(PORTB, 23UL, kPORT_MuxAlt5); /* SDRAM_D28*/

PORT_SetPinMux(PORTC, 12UL, kPORT_MuxAlt5); /* SDRAM_D27*/

PORT_SetPinMux(PORTC, 13UL, kPORT_MuxAlt5); /* SDRAM_D26*/

PORT_SetPinMux(PORTC, 14UL, kPORT_MuxAlt5); /* SDRAM_D25*/

PORT_SetPinMux(PORTC, 15UL, kPORT_MuxAlt5); /* SDRAM_D24*/

PORT_SetPinMux(PORTC, 24UL, kPORT_MuxAlt5); /* SDRAM_D5/FB_A5*/

PORT_SetPinMux(PORTC, 25UL, kPORT_MuxAlt5); /* SDRAM_D4/FB_A4*/

PORT_SetPinMux(PORTC, 26UL, kPORT_MuxAlt5); /* SDRAM_D3/FB_A3*/

PORT_SetPinMux(PORTC, 27UL, kPORT_MuxAlt5); /* SDRAM_D2/FB_A2*/

PORT_SetPinMux(PORTC, 28UL, kPORT_MuxAlt5); /* SDRAM_D1/FB_A1*/

PORT_SetPinMux(PORTC, 29UL, kPORT_MuxAlt5); /* SDRAM_D0/FB_A0*/

/* SDRAM Address*/

PORT_SetPinMux(PORTB, 18UL, kPORT_MuxAlt5); /* SDRAM_A23*/

PORT_SetPinMux(PORTC, 0UL, kPORT_MuxAlt5); /* SDRAM_A22*/

PORT_SetPinMux(PORTC, 1UL, kPORT_MuxAlt5); /* SDRAM_A21*/

PORT_SetPinMux(PORTC, 2UL, kPORT_MuxAlt5); /* SDRAM_A20*/

PORT_SetPinMux(PORTC, 4UL, kPORT_MuxAlt5); /* SDRAM_A19*/

PORT_SetPinMux(PORTC, 5UL, kPORT_MuxAlt5); /* SDRAM_A18*/

PORT_SetPinMux(PORTC, 6UL, kPORT_MuxAlt5); /* SDRAM_A17*/

PORT_SetPinMux(PORTC, 7UL, kPORT_MuxAlt5); /* SDRAM_A16*/

PORT_SetPinMux(PORTC, 8UL, kPORT_MuxAlt5); /* SDRAM_A15*/

PORT_SetPinMux(PORTC, 9UL, kPORT_MuxAlt5); /* SDRAM_A14*/

PORT_SetPinMux(PORTC, 10UL, kPORT_MuxAlt5); /* SDRAM_A13*/

PORT_SetPinMux(PORTD, 2UL, kPORT_MuxAlt5); /* SDRAM_A12*/

PORT_SetPinMux(PORTD, 3UL, kPORT_MuxAlt5); /* SDRAM_A11*/

PORT_SetPinMux(PORTD, 4UL, kPORT_MuxAlt5); /* SDRAM_A10*/

PORT_SetPinMux(PORTD, 5UL, kPORT_MuxAlt5); /* SDRAM_A9*/


PORT_SetPinMux(PORTD, 7UL, kPORT_MuxAlt5);


PORT_SetPinMux(PORTC, 16UL, kPORT_MuxAlt5); /* SDRAM_DQM2*/

PORT_SetPinMux(PORTC, 17UL, kPORT_MuxAlt5); /* SDRAM_DQM3*/

PORT_SetPinMux(PORTC, 18UL, kPORT_MuxAlt5); /* SDRAM_DQM1*/

PORT_SetPinMux(PORTC, 19UL, kPORT_MuxAlt5); /* SDRAM_DQM0*/


/* Flexbus high address */

PORT_SetPinMux(PORTD, 8UL, kPORT_MuxAlt6); /* FB_A16*/

PORT_SetPinMux(PORTD, 9UL, kPORT_MuxAlt6); /* FB_A17*/

PORT_SetPinMux(PORTD, 10UL, kPORT_MuxAlt6); /* FB_A19*/

PORT_SetPinMux(PORTD, 11UL, kPORT_MuxAlt6); /* FB_A19*/

PORT_SetPinMux(PORTD, 12UL, kPORT_MuxAlt6); /* FB_A20*/

PORT_SetPinMux(PORTD, 13UL, kPORT_MuxAlt6); /* FB_A21*/

PORT_SetPinMux(PORTD, 14UL, kPORT_MuxAlt6); /* FB_A22*/

PORT_SetPinMux(PORTD, 15UL, kPORT_MuxAlt6); /* FB_A23*/

PORT_SetPinMux(PORTA, 29UL, kPORT_MuxAlt6); /* FB_A24*/

PORT_SetPinMux(PORTA, 28UL, kPORT_MuxAlt6); /* FB_A25*/


/* Flexbus RW, OE, chip select and etc signal */

PORT_SetPinMux(PORTB, 19UL, kPORT_MuxAlt5); /* FB_OE_b*/

PORT_SetPinMux(PORTC, 11UL, kPORT_MuxAlt5); /* FB_RW_b*/

PORT_SetPinMux(PORTD, 0UL, kPORT_MuxAlt5); /* FB_CS1_b*/

PORT_SetPinMux(PORTD, 1UL, kPORT_MuxAlt5); /* FB_CS0_b*/