Eureka,
We success in display first acquisition from adv7282-m device.
We set Virtual Channel #1 under ADV7282-m with adv7282_csi_write(0x0D,0x40) command and we finally use ipu_id=0 and csi_id=1 configuration to capture video over mipi bus.
Now we have synchro problem and pixel frequency acquisition problem.
The current device tree configuration is :
v4l2_cap_1 {
compatible = "fsl,imx6q-v4l2-capture";
ipu_id = <0>; /* IPU1 selected */
csi_id = <1>; /* virtual channel1 selected */
mclk_source = <0>;
mipi_camera = <1>;
status = "okay";
};
&mipi_csi{
status = "okay";
ipu_id = <0>; /* IPU1 is selected */
csi_id = <1>; /* CSI0/channel1 is selected */
v_channel = <1>; /* virtual channel1 selected */
lanes = <1>; /* only one lane */
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
adv7282-m {
compatible = "adv7282";
pinctrl-names = "default";
reg = <0x21>;
csi_id = <1>;
cvbs = <1>; /* ANALOGIC channel INPUT#1 */
DOVDD-supply = <®_3p3v>; // 3.3v
AVDD-supply = <®_3p3v>; // 1.8v
DVDD-supply = <®_3p3v>; // 1.8v
PVDD-supply = <®_3p3v>; // 1.8v
clocks = <&clks 200>;
clock-names = "csi_mclk";
mipi_camera = <1>; /* Needed for v4l2 configuration */
ipu_id = <0>; /* IPU1 selected */
status = "okay";
};
};
We use PAL video signal and we test without adv7282 progressive format, and with progressive format (mipi clock is double). In these two adv7282 configuration case, we don't reach to synchronise output display image acquisition.
The ADV7282-M output data is 8-bit YCrCb 4:2:2 format with one lane.
Routing MIPI stream into CSI2 is Ok.
It displays :
gst-launch-1.0 --gst-debug=*:1 -v imxv4l2src device=/dev/video0 ! imxv4l2sink
====== IMXV4L2SRC: 4.0.8 build on Jul 13 2016 15:19:44. ======
====== IMXV4L2SINK: 4.0.8 build on Jul 13 2016 15:19:44. ======
Setting pipeline to PAUSED ...
display(/dev/fb0) resolution is (1024x768).
Pipeline is live and does not need PREROLL ...
Setting pipeline to PLAYING ...
New clock: GstSystemClock
/GstPipeline:pipeline0/GstImxV4l2Src:imxv4l2src0.GstPad:src: caps = "video/x-raw\,\ format\=\(string\)NV12\,\ width\=\(int\)720\,\ height\=\(int\)576\,\ framerate\=\(fraction\)25/1\,\ interlace-mode\=\(string\)interleaved"
/GstPipeline:pipeline0/GstImxV4l2Sink:imxv4l2sink0.GstPad:sink: caps = "video/x-raw\,\ format\=\(string\)NV12\,\ width\=\(int\)720\,\ height\=\(int\)576\,\ framerate\=\(fraction\)25/1\,\ interlace-mode\=\(string\)interleaved"
v4l2sink need allocate 3 buffers.
Colors are wrong and there is also a vertical scrolling (see mp4 file).
We don't know if we have iMX6 IPU or V4L2 configuration to complete or change.
We study "MIPI–CSI2 Peripheral on i.MX6 MPUs" freescale document and we noticed the current status :
IPU1_IDMAC_CH_EN_1(0x2608004) = 0x00201002 --> IDMAC channel is enabled,
IPU1_CH_DB_MODE_SEL1(@0x2600154) = 0x00000002 --> Double buffer is used for this channel.
IPU1_CONF(@0x2600000) = 0x20000106 --> CSI0 selected, mipi connected to CSI1, ic is enable, csi1 is enable,
IPU1_SMFC_MAP(@0x2650000) = 0x00000028 --> CSI0, ID=1 mapped to DMASMFC channel 1
IPU1_SMFC_BS(@0x2650008) = 0x00000070 --> Burst Size of SMFCDMA channel 1 = 8-1
IPU1_CSI1_SENS_CONF(@0x2638000) =0x04000A30 --> YUV422 8 bits per color, CCIR interlaced mode (BT.656)
IPU1_CSI1_SENS_FRM_SIZE(@0x2638004) =0x027002CF --> row=625-1, width=720-1
IPU1_CSI1_ACT_FRM_SIZE(@0x2638008) =0x023F02CF --> row=576-1, width=720-1
IPU1_CSI1_OUT_FRM_CTRL(@0x263800C) =0x00000000
Is MIPI/IPU settings have to match with 640x480@15 configuration ?
How can I check IPU configuration ?
Regards,
Gabriel Grange
