Hi, Karthik,
If you do not use external crystal or clock source from EXTAL0/Xtal0 pins, you have to use internal clock source. First of all, the internal PLL can NOT output 180mhz clock signal, you have to use PLL plus internal clock source. For K66, I think you can use 48MHz interncl clock source and PLL so that PLL can output 180MHz clock signal.
But for your case, now that you have 50MHz clock source connected to EXTAL0, why do you use it to generate 180mHz clock signal as core/system clock source.
As you know that the PLL input clock frequency is limited from 8MHz~16mHz, Pls refer to Figure 27-1. Multipurpose Clock Generator (MCG) block diagram in RM of K66.
You select the OSC0 clock source which is 50MHz, PRDIV=4, the PLL input clock source is 50MHz/(4+1)=10MHz. set VDIV=5b'00010(multiply is 18), the VCO output clock is (50MHz/5)*18*2=360MHz, the VCO/2=180MHz, which is core/system clock.
Regarding the code, I think you can create a simple project based KDS tools, select the TWR-K65, the tools can generate the clock code. If you define the #define CLOCK_SETUP 1 in system_MK65F18.h, the MCG will use PEE mode and generate 180MHz as core/system clock. If you use K66, you can copy the snippet of the code. Before you use the code, pls check the MCG register setting based on your input clock from EXTAL pin.
Hope it can help you
BR
XiangJun Rong