lpcware

Transfer data from parallel GPIO using GPDMA

Discussion created by lpcware Employee on Jun 15, 2016
Latest reply on Jun 15, 2016 by lpcware
Content originally posted in LPCWare by marco on Fri Jul 27 05:55:22 MST 2012
Hi everyone
(sorry for my English!!)
I'm trying to transfer 8bit parallel data input from GPIO pins to SRAM using GPDMA on LPC1850 at 180mhz CCLK. The DMA request is made by counter match.

When I enable the DMA Channel, the Error Interrupt (INTERRSTAT) is asserted, and the DMA channel is disabled.
If I set the SRCADDR register of Channel0 on a FLASH address or a SRAM address the transfer is enabled and properly terminated.
I don't understand what's wrong in the SRCADDR when I initialize it with GPIO PORT.
Below there is my GPDMA initialization.




// Enable clock and init GPIO inputs
LPC_CCU1->CLK_M3_GPIO_CFG  = (1<<1) | (1<<0);      //enable clock
while (!(LPC_CCU1->CLK_M3_GPIO_STAT & (1<<1)));     //stat run

//for all pins on port 4 I configure input
//...
LPC_SCU->SFSP9_0  = (0 << 0) |     //Function 0 GPIO
                                   (2 << 3) |  //Disable pullup and pulldown
                                   (1 << 5) |  //Fast speed
                                   (1 << 6) |  //Enable input buffer
                                   (1 << 7);   //Disable input glitch filter
//...

LPC_CCU1->CLK_M3_DMA_CFG  = (1<<1) | (1<<0);   //enable clock
while (!(LPC_CCU1->CLK_M3_DMA_STAT & (1<<1)));   //check stat run

// Reset all channel configuration register
LPC_GPDMA->C0CONFIG = 0;
LPC_GPDMA->C1CONFIG = 0;
LPC_GPDMA->C2CONFIG = 0;
LPC_GPDMA->C3CONFIG = 0;
LPC_GPDMA->C4CONFIG = 0;
LPC_GPDMA->C5CONFIG = 0;
LPC_GPDMA->C6CONFIG = 0;
LPC_GPDMA->C7CONFIG = 0;

// Clear all DMA interrupt and error flag
LPC_GPDMA->INTTCCLEAR = 0xFF;    //Clear CH0 Count Interrupt flag
LPC_GPDMA->INTERRCLR = 0xFF;    //Clear CH0 Error Interrupt flag  
   
// Clear DMA configure
LPC_GPDMA->C0CONTROL = 0x00;
LPC_GPDMA->C0CONFIG = 0x00;

// Assign Linker List Item value
LPC_GPDMA->C0LLI = 0;

//Assign source address GPIO on port 4
LPC_GPDMA->C0SRCADDR    = (uint32_t) &LPC_GPIO_PORT->PIN[4];
//Assign destination address dest1[256] buffer in SRAM
LPC_GPDMA->C0DESTADDR    = (uint32_t) dest1;

LPC_GPDMA->C0CONTROL    = (uint32_t)(256    //transfer size
            | (0 << 12)                //source burst size - 1
            | (0 << 15)                //destination burst size - 1
            | (0 << 18)                //source width - 8bit
            | (0 << 21)                //dest width - 8bit
            | (0 << 24)
            | (0 << 25)
            | (0 << 26)                //source increment - do not inc
            | (1 << 27)                //destination increment - inc
            | (0 << 28)
            | (0 << 29)
            | (0 << 30)
            | (1 << 31));                //terminal count interrupt - enabled

LPC_GPDMA->CONFIG = 1;                //Enable GPDMA Controller
while (!(LPC_GPDMA->CONFIG & 1));    //check enable
   
LPC_GPDMA->C0CONFIG = 0         //Channel Disable
                | ((1 & 0x1f) << 1)                //source peripheral - Cap0_2
                | (0 << 6)                              //dest request memory - none
                | (2 << 11)                            //flow control - peripheral to memory
                | (1 << 14)                           //(14) - mask out error interrupt
                | (1 << 15)                           //(15) - mask out terminal count interrupt
                | (0 << 16)                          //(16) - no locked transfers
                | (0 << 18);                        //(18) - no HALT
               
//Enable GPDMA interrupt
NVIC_EnableIRQ(DMA_IRQn);
   
LPC_GPDMA->C0CONFIG |= 1;                    //Channel Enable
//Here i received an interrupt error (LPC_GPDMA->INTERRSTAT=1) and the DMA Channel is disabled

Can anyone help me for a correct acquisition and DMA initialization?
Thanks in advance.

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