Content originally posted in LPCWare by igorsk on Mon Oct 10 04:26:54 MST 2011
Quote: klatecki
I understand this but I think compiler should knows that Cortex M0 don't support mis-aligned read and should use multiple reads instead of use incorrect instruction that cause Hard Fault
The compiler can't know what you intend. Since the structure is volatile, it [I]probably[/I] means that field accesses should be atomic, and that's what it's trying to do here.
Quote: klatecki
In the specific (more complex) situations (eg, casting the raw data buffer on the structure), the compiler does not report warning. I will try to create such an example in which the compiler will not warn you and still be an issue.
Use memcpy to a local variable if you're not sure of the original alignment.