LPC4370 ACDHS speed

[lpcware]

Content originally posted in LPCWare by dmorse on Fri Jan 24 09:24:01 MST 2014
How do I set up the BASE_M4_CLK or the AHB clocks for high speed ADC?

How do I verify the BASE_ADCHS_CLK is running (204Mhz ) fast enough for 80Msample?

I have the ADCHS running but the max I can sample is 2Khz.

[lpcware]

Content originally posted in LPCWare by nmz787 on Sat Aug 30 02:04:02 MST 2014
Did you go through the code references I sent you?

In previous comments it is mentioned that you can do this:
Chip_Clock_GetRate(CLK_ADCHS)

[lpcware]

Content originally posted in LPCWare by Trung Thanh on Fri Aug 29 23:37:54 MST 2014

---

Quote: nmz787
Have you tried the code here:
http://www.lpcware.com/content/forum/lpc4370-acdhs-speed#comment-1135033

?

---

Have you tried that code?
I tried that and I went i send "a" by computer i just get "<0>" for one time?
And i want to find the way get data form ADCHS??
It don't like ADC on the other microcontroller have data register???

[lpcware]

Content originally posted in LPCWare by nmz787 on Wed Aug 27 13:28:04 MST 2014
have you tried grepping the libopencm3 codebase for the registers?
https://github.com/libopencm3/libopencm3

I know you're already using keil, but just in case, for comparison, here is how to use LPC Link V2 with libopencm3:
https://github.com/libopencm3/libopencm3-examples/pull/59/files

Also some demo files here:
http://www.diolan.com/lpc4300.html

Also, I hope you have the UM10503 User Manual, to search that for the register names, to get their address/offset.


Between the LPCware demos, the diolan demos, libopencm3, and the UM10503 PDF, I was able to figure out the naming convention LPCware uses and how to set things up.

[lpcware]

Content originally posted in LPCWare by Trung Thanh on Tue Aug 26 11:40:48 MST 2014

---

Quote: akmarov
Finally I've got some adequate results. ADCHS clock is 80MHz, but sample rate is only 40Msps, not 80Msps as I expected. Every time I've tried to set SAMPLERATE to values more than 4000000 - UART stopped working. Is it real to get 80Msps?

I've added my version of hsadc.c . It is just a composition of what dmorse and sundarapandian have done, and it can be compiled in Keil 4.73 without errors.

---

How can you know Check ADCHS clock is 80Mhz and Check Sample Rate in KeilC Complier?
I used unlink2 to debuger.

Thanks

[lpcware]

Content originally posted in LPCWare by Trung Thanh on Sat Aug 23 08:15:40 MST 2014

---

Quote: wellsk
The periph_hsadc example needs to work on multiple boards and those boards all have different clock setups. The example, with it's complex clock setup, tries to work on all those boards by determing at run-time what the clock tree looks like.

But in reality, the HSADC clock structure is very simple and can be setup by directly setting the HSADC base clock with this one function:

Chip_Clock_SetBaseClock(CLK_BASE_ADCHS, <SOME CLOCK INPUT>, true, false);

You can attach the HSADC base clock to any of the following clock inputs:

/**
 * @brief CGU clock input list
 * These are possible input clocks for the CGU and can come
 * from both external (crystal) and internal (PLL) sources. These
 * clock inputs can be routed to the base clocks (@ref CHIP_CGU_BASE_CLK_T).
 */
typedef enum CHIP_CGU_CLKIN {
CLKIN_32K,/*!< External 32KHz input */
CLKIN_IRC,/*!< Internal IRC (12MHz) input */
CLKIN_ENET_RX,/*!< External ENET_RX pin input */
CLKIN_ENET_TX,/*!< External ENET_TX pin input */
CLKIN_CLKIN,/*!< External GPCLKIN pin input */
CLKIN_RESERVED1,
CLKIN_CRYSTAL,/*!< External (main) crystal pin input */
CLKIN_USBPLL,/*!< Internal USB PLL input */
CLKIN_AUDIOPLL,/*!< Internal Audio PLL input */
CLKIN_MAINPLL,/*!< Internal Main PLL input */
CLKIN_RESERVED2,
CLKIN_RESERVED3,
CLKIN_IDIVA,/*!< Internal divider A input */
CLKIN_IDIVB,/*!< Internal divider B input */
CLKIN_IDIVC,/*!< Internal divider C input */
CLKIN_IDIVD,/*!< Internal divider D input */
CLKIN_IDIVE,/*!< Internal divider E input */
CLKINPUT_PD/*!< External 32KHz input */
} CHIP_CGU_CLKIN_T;

---

Quote:

This shows the fADC is 12Mhz:

//Chip_Clock_GetRate(CLK_ADCHS)
  freq = Chip_Clock_GetRate(CLK_ADCHS);

---

If you are getting 12Mhz from the HSADC peripheral clock read functions, your base clock is likely the 12MHz IRC or external oscillator.

You will have to work a little bit to get an exact 80Mhz to the HSADC. The easiest way to do it would be to setup the audio PLL to 80MHz and use it as HSADC base clock. This would require you to use the tool at http://www.lpcware.com/content/nxpfile/audio-pll-settings-calculation-tool to get the audio PLL coefficients with the audio PLL setup functions.

Here are some other possibilities that won't give you an exact 80MHz: There are 5 possible dividers in the 18xx/43xx you can use, but some of these might be used for other functions (ie, board setup code normally uses divider E for SPIFI clocking setup). If setting up a divider causes the system to crash, try using another divider.

Option 1: Connect the 204MHz main PLL to a divider input, set the divider to 3, and use the divider for the HSADC base clock. Gives 204 / 3 = 68Mhz.
Just make sure you aren't using those dividers for anything else!

Chip_Clock_SetDivider(CLK_IDIV_A, CLKIN_MAINPLL, 3); /* Setup divider A for main PLL rate divided by 3 */
Chip_Clock_SetBaseClock(CLK_BASE_ADCHS, CLKIN_IDIVA, true, false); /* HSADC base clock = divider A input */

[WARNING: DO NOT USE THE OPTION 2 SEE POSTS BELOW FOR MORE INFORMATION]
Option 2: Use the USB PLL rate (typically 480MHz) with a divide by 6 to get 80MHz. (Note different dividers have different maximum divider values)

Chip_USB0_Init(); /* Sets USB PLL to 480Mhz */
Chip_Clock_SetDivider(CLK_IDIV_D, CLKIN_USBPLL, 6); /* Setup divider D for USB PLL rate divided by 6 */
Chip_Clock_SetBaseClock(CLK_BASE_ADCHS, CLKIN_IDIVD, true, false); /* HSADC base clock = divider D input */

You can use the Chip_Clock_GetRate(CLK_ADCHS) to get the clock rate the HSADC is currently running at regardless of clock tree configuration.

---

I used lib 's KeilC provid for lpc4370 (startup_Lpc43xx.s and system_Lpc43xx.c) but i can't find BASE_ADCHS_CLK register in CGU block.
How can i setup  BASE_ADCHS_CLK register in system_Lpc43xx.c and How can i check BASE_ADCHS_CLK register's values when i set it?

Thanks

[lpcware]

Content originally posted in LPCWare by Trung Thanh on Thu Aug 21 06:51:12 MST 2014
yes i have.
But the problem is I usually set every register to easy configured.

In hsadc.c of NXP they write:
typedef struct {/*!< (@ 0x40050000) CGU Structure          */
__I  uint32_t  RESERVED0[5];
__IO uint32_t  FREQ_MON;/*!< (@ 0x40050014) Frequency monitor register */
__IO uint32_t  XTAL_OSC_CTRL;/*!< (@ 0x40050018) Crystal oscillator control register */
CGU_PLL_REG_T  PLL[CGU_AUDIO_PLL + 1];/*!< (@ 0x4005001C) USB and audio PLL blocks */
__IO uint32_t  PLL0AUDIO_FRAC;/*!< (@ 0x4005003C) PLL0 (audio)           */
__I  uint32_t  PLL1_STAT;/*!< (@ 0x40050040) PLL1 status register   */
__IO uint32_t  PLL1_CTRL;/*!< (@ 0x40050044) PLL1 control register  */
__IO uint32_t  IDIV_CTRL[CLK_IDIV_LAST];/*!< (@ 0x40050048) Integer divider A-E control registers */
__IO uint32_t  BASE_CLK[CLK_BASE_LAST];/*!< (@ 0x4005005C) Start of base clock registers */
} LPC_CGU_T;




and in system_LPC43xx of KeilC :

typedef struct {                                    /*!< (@ 0x40050000) CGU Structure                                          */
  __I  uint32_t  RESERVED0[5];
  __IO uint32_t  FREQ_MON;                          /*!< (@ 0x40050014) Frequency monitor register                             */
  __IO uint32_t  XTAL_OSC_CTRL;                     /*!< (@ 0x40050018) Crystal oscillator control register                    */
  __I  uint32_t  PLL0USB_STAT;                      /*!< (@ 0x4005001C) PLL0USB status register                                */
  __IO uint32_t  PLL0USB_CTRL;                      /*!< (@ 0x40050020) PLL0USB control register                               */
  __IO uint32_t  PLL0USB_MDIV;                      /*!< (@ 0x40050024) PLL0USB M-divider register                             */
  __IO uint32_t  PLL0USB_NP_DIV;                    /*!< (@ 0x40050028) PLL0USB N/P-divider register                           */
  __I  uint32_t  PLL0AUDIO_STAT;                    /*!< (@ 0x4005002C) PLL0AUDIO status register                              */
  __IO uint32_t  PLL0AUDIO_CTRL;                    /*!< (@ 0x40050030) PLL0AUDIO control register                             */
  __IO uint32_t  PLL0AUDIO_MDIV;                    /*!< (@ 0x40050034) PLL0AUDIO M-divider register                           */
  __IO uint32_t  PLL0AUDIO_NP_DIV;                  /*!< (@ 0x40050038) PLL0AUDIO N/P-divider register                         */
  __IO uint32_t  PLL0AUDIO_FRAC;                    /*!< (@ 0x4005003C) PLL0AUDIO fractional divider register                  */
  __I  uint32_t  PLL1_STAT;                         /*!< (@ 0x40050040) PLL1 status register                                   */
  __IO uint32_t  PLL1_CTRL;                         /*!< (@ 0x40050044) PLL1 control register                                  */
  __IO uint32_t  IDIVA_CTRL;                        /*!< (@ 0x40050048) Integer divider A control register                     */
  __IO uint32_t  IDIVB_CTRL;                        /*!< (@ 0x4005004C) Integer divider B control register                     */
  __IO uint32_t  IDIVC_CTRL;                        /*!< (@ 0x40050050) Integer divider C control register                     */
  __IO uint32_t  IDIVD_CTRL;                        /*!< (@ 0x40050054) Integer divider D control register                     */
  __IO uint32_t  IDIVE_CTRL;                        /*!< (@ 0x40050058) Integer divider E control register                     */
  __I  uint32_t  BASE_SAFE_CLK;                     /*!< (@ 0x4005005C) Output stage 0 control register for base clock
                                                         BASE_SAFE_CLK                                                         */
  __IO uint32_t  BASE_USB0_CLK;                     /*!< (@ 0x40050060) Output stage 1 control register for base clock
                                                         BASE_USB0_CLK                                                         */
  __IO uint32_t  BASE_PERIPH_CLK;                   /*!< (@ 0x40050064) Output stage 2 control register for base clock
                                                         BASE_PERIPH_CLK                                                       */
  __IO uint32_t  BASE_USB1_CLK;                     /*!< (@ 0x40050068) Output stage 3 control register for base clock
                                                         BASE_USB1_CLK                                                         */
  __IO uint32_t  BASE_M4_CLK;                       /*!< (@ 0x4005006C) Output stage BASE_M4_CLK control register              */
  __IO uint32_t  BASE_SPIFI_CLK;                    /*!< (@ 0x40050070) Output stage BASE_SPIFI_CLK control register           */
  __IO uint32_t  BASE_SPI_CLK;                      /*!< (@ 0x40050074) Output stage BASE_SPI_CLK control register             */
  __IO uint32_t  BASE_PHY_RX_CLK;                   /*!< (@ 0x40050078) Output stage BASE_PHY_RX_CLK control register          */
  __IO uint32_t  BASE_PHY_TX_CLK;                   /*!< (@ 0x4005007C) Output stage BASE_PHY_TX_CLK control register          */
  __IO uint32_t  BASE_APB1_CLK;                     /*!< (@ 0x40050080) Output stage BASE_APB1_CLK control register            */
  __IO uint32_t  BASE_APB3_CLK;                     /*!< (@ 0x40050084) Output stage BASE_APB3_CLK control register            */
  __IO uint32_t  BASE_LCD_CLK;                      /*!< (@ 0x40050088) Output stage BASE_LCD_CLK control register             */
  __I    uint32_t  RESERVED1;

(I think they have to Define __IO uint32_t  BASE_ADCHS_CLK )
But i don't know how to make it

  __IO uint32_t  BASE_SDIO_CLK;                     /*!< (@ 0x40050090) Output stage BASE_SDIO_CLK control register            */
  __IO uint32_t  BASE_SSP0_CLK;                     /*!< (@ 0x40050094) Output stage BASE_SSP0_CLK control register            */
  __IO uint32_t  BASE_SSP1_CLK;                     /*!< (@ 0x40050098) Output stage BASE_SSP1_CLK control register            */
  __IO uint32_t  BASE_UART0_CLK;                    /*!< (@ 0x4005009C) Output stage BASE_UART0_CLK control register           */
  __IO uint32_t  BASE_UART1_CLK;                    /*!< (@ 0x400500A0) Output stage BASE_UART1_CLK control register           */
  __IO uint32_t  BASE_UART2_CLK;                    /*!< (@ 0x400500A4) Output stage BASE_UART2_CLK control register           */
  __IO uint32_t  BASE_UART3_CLK;                    /*!< (@ 0x400500A8) Output stage BASE_UART3_CLK control register           */
  __IO uint32_t  BASE_OUT_CLK;                      /*!< (@ 0x400500AC) Output stage 20 control register for base clock
                                                         BASE_OUT_CLK                                                          */
  __I  uint32_t  RESERVED2[4];
  __IO uint32_t  BASE_APLL_CLK;                     /*!< (@ 0x400500C0) Output stage 25 control register for base clock
                                                         BASE_APLL_CLK                                                         */
  __IO uint32_t  BASE_CGU_OUT0_CLK;                 /*!< (@ 0x400500C4) Output stage 25 control register for base clock
                                                         BASE_CGU_OUT0_CLK                                                     */
  __IO uint32_t  BASE_CGU_OUT1_CLK;                 /*!< (@ 0x400500C8) Output stage 25 control register for base clock
                                                         BASE_CGU_OUT1_CLK                                                     */
} LPC_CGU_Type;

[lpcware]

Content originally posted in LPCWare by nmz787 on Wed Aug 20 21:10:31 MST 2014
Have you tried the code here:
http://www.lpcware.com/content/forum/lpc4370-acdhs-speed#comment-1135033

?

[lpcware]

Content originally posted in LPCWare by Trung Thanh on Wed Aug 20 08:31:29 MST 2014
Hello everybody!

In Lpc43xx's usermanual,
Table 1115.ADCHS clocking and power control
                                Base clock                    Branch clock                    Operating frequency                     Notes
AHB clock                BASE_M4_CLK            CLK_M4_ADCHS up to     204 MHz.                                       For register interface.                  ADCHS clock           BASE_ADCHS_CLK       CLK_ADCHS                   up to 80MHz                                  For conversion rate.

But I can't file in file systerm_LPC43xx.c of Keil C Lib in CGU block.
and i check in NXP's sample with Keil C complie and get the same result?
I debug CGU block and I can't found   BASE_ADCHS_CLK In CGU block?
I think I can easy set like this: LPC_CGU-> BASE_ADCHS_CLK = ....

Please help Me

[lpcware]

Content originally posted in LPCWare by sundarapandian on Thu Jun 12 19:29:24 MST 2014
Posted a warning message informing not to use Option 2.

[lpcware]

Content originally posted in LPCWare by David Lee on Thu Jun 12 11:20:17 MST 2014
Would it be possible to mark Option 2 as incorrect?

This would save alot of time for those of us who did not read past this post from NXP Support.

David

[lpcware]

Content originally posted in LPCWare by dmorse on Mon Feb 03 14:19:44 MST 2014
The original hsadc.c file used TIMER1 to trigger a software event to trigger to start the ADC. In my modification I tried to us the TIMMER1 to stop the ADC sampling but it did not work. I found that there were too many IRQ events (with higher priority than the  UART) causing the UART not to get service and also the descriptor would not update. I left the code in and set the SAMPLERATE  to 100 which cause TIMER1 to file every 10ms. I used this to toggle GPIO port 3 bit 7 for testing.

[lpcware]

Content originally posted in LPCWare by nmz787 on Sat Feb 01 21:18:36 MST 2014
well max CPU clock is 204 MHz, right? Can you try setting the ADC clock to 160MHz or something around there?

[lpcware]

Content originally posted in LPCWare by akmarov on Sat Feb 01 09:20:34 MST 2014
Finally I've got some adequate results. ADCHS clock is 80MHz, but sample rate is only 40Msps, not 80Msps as I expected. Every time I've tried to set SAMPLERATE to values more than 4000000 - UART stopped working. Is it real to get 80Msps?

I've added my version of hsadc.c . It is just a composition of what dmorse and sundarapandian have done, and it can be compiled in Keil 4.73 without errors.

[lpcware]

Content originally posted in LPCWare by akmarov on Fri Jan 31 16:10:31 MST 2014
Really? I've viewed the code that you gave to me earlier (http://www.lpcware.com/system/files/hsadc_0.c) and found this:

/* Select both positive and negative DC biasing for input 3 */
Chip_HSADC_SetACDCBias(LPC_ADCHS, 1, HSADC_CHANNEL_NODCBIAS, HSADC_CHANNEL_NODCBIAS);

but this is not related to input 3, it is related to input 1.

[lpcware]

Content originally posted in LPCWare by dmorse on Fri Jan 31 14:19:16 MST 2014
I used ADC0 and ADC3 as differential.
J4 pin 4 as the Pos input and J4 pin 10 as Neg input.

[lpcware]

Content originally posted in LPCWare by akmarov on Fri Jan 31 12:14:42 MST 2014
I've managed to compile your code and load it in microcontroller, but I don't understand what HSADC input do you use.

[lpcware]

Content originally posted in LPCWare by dmorse on Fri Jan 31 08:49:43 MST 2014
This was done in the LPCXpresso IDE.

char countC[32} = "";

This just creates a null string the size of 32 chars;
I did it this way because I could figure out how to declare a string in C.
The code is C not CPP..

[lpcware]

Content originally posted in LPCWare by akmarov on Fri Jan 31 07:11:45 MST 2014
dmorse, I can't compile the project with your modified hsadc.c in Keil 4.73. I've got 14 errors, all looks like this: 
#268: declaration may not appear after executable statement in block char countC[32] = "";///

[lpcware]

Content originally posted in LPCWare by nmz787 on Fri Jan 31 00:18:05 MST 2014
Glad to see you're making progress!

The LabTool code uses DMA, though they're using USB (the driver is provided by NXP, and the GUI source is provided too, with instructions for how to build on Windows. GUI readme:
https://github.com/embeddedartists/labtool/blob/master/app/COMPILE.md

Wow and there's even a lookup table for the PLL frequencies;
https://github.com/embeddedartists/labtool/blob/master/fw/program/source/capture.c#L115

Here's the DMA IRQ:
https://github.com/embeddedartists/labtool/blob/master/fw/program/source/capture_vadc.c#L198

Here's the DMA setup:
https://github.com/embeddedartists/labtool/blob/master/fw/program/source/capture_vadc.c#L468

Searching the labtool/fw/program directory with

grep -r DMA ./ |grep -v \.h |cut -d':' -f 1|uniq

outputs this list of files that refer to DMA (not including .h files, that's what the grep -v \.h gets rid of):

./sct/sct_fsm.c
./source/capture_sgpio.c
./source/capture_vadc.c
./source/generator_sgpio.c
./source/main.c
./source/startup_LPC43xx.s
./uVision/Internal_SRAM/firmware.map
./uVision/Internal_SRAM/startup_lpc43xx.lst

Best of luck, let us know when you get somewhere! I wish I had more time to program these days, but glad to help pull data together for others! When my class ends in a few months I'll be able to get to programming more!

[lpcware]

Content originally posted in LPCWare by dmorse on Thu Jan 30 12:59:37 MST 2014
Thanks you, That worked I now have ADCHS clock = 80MHz.