lpcware

M4-M0 core synchronisation / lock mechanism using mutex or semaphore

Discussion created by lpcware Employee on Jun 15, 2016
Latest reply on Jun 16, 2016 by lpcware
Content originally posted in LPCWare by wlamers on Fri Jul 18 01:06:35 MST 2014
I have an application in which both the M4 and M0 core (of an LPC4357) are accessing a (kind of) ring buffer. The buffer is used to store and retrieve data using a pointer mechanism. This requires a sort of lock mechanism preventing simultaneous access of both cores to the pointers/variables. As a side note: there are also some interrupts (mainly on the M4 core) that also access the same buffer pointers/variables.

The latter situation (interrupts) can de dealt with by disabling the interrupts while entering a critical section (section that access the buffer pointers/variables). But the M4-M0 synchronisation is more difficult. I do not want to use the SEV instruction to signal an interrupt to the other core to handle the lock mechanism, mainly due to performance reasons.

At the moment if have implement a simple lock mechanism that reads a lock variable in shared memory, accessible by both cores. The problem is that the 'check and set' of the lock variable isn't an atomic operation (it requires an 'if' statement and an assignment). This could possible break the lock mechanism causing unpredictable behaviour.

Therefore I need to implement a classic mutex lock mechanism where the test and set of the lock variable (mutex) is atomic. For the M4 this should be possible using the LDREX and STREX (load-exclusive, store-exclusive) instructions. Also ARM recommends using DMB to set a memory barrier. But oddly enough the M0 does NOT have these instructions. Rendering it impossible to use a mutex or other lock mechanism between the cores. Obviously NXP did know this during the design op the 43xx family and I assume they have come up with a solution. Although I cannot seem to find one. The IPC section of the manual and the application note is of no help, nor do I find much information on the internet.

So to generalize my question: who knows a good way to design an 'atomic' lock mechanism between the two cores (which can also be used in the interrupt service routines)?

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