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EMC generates double read cycles for static chip selects.

Question asked by lpcware Employee on Jun 15, 2016
Latest reply on Oct 15, 2016 by jizhou Zhang
Content originally posted in LPCWare by Grant.Edwards on Mon Jun 10 09:58:11 MST 2013

I'm having problems getting the LPC1857 EMC configured for use with static peripherals (e.g. external UARTs with 8 or 16-bit wide parallel bus interfaces).


The write cycle configuration appears to work exactly as described in the LPC18xx user manual. However, the read cycle is usually (but not always) twice as long as I've configured. In addition, one or more address lines will change stage half-way through the "double-length" read cycle. The EMC appears to be attempting to read two adjacent addresses every time I do a single read.


The "double length" read doesn't occur all of the time. Perhaps 5% of the time, the read cycle will be the correct length and behave exactly as described in the user manual. AFAICT, whether I get a correct read cycle or a double-length read cycle is completely random. The exact same instruction reading the exact same address can generate a double-length read cycle one time through a loop and a correct read the next time.


I have disabled both page mode and buffering.


Reads are doubled both with and without "extended wait", and regardless of BLS configuration.


I've verified that the code is doing a single ldr.b instruction to read a peripheral register via an 8-bit wide chip select and an ldr.h instruction to read a peripheral register via a 16-bit wide chip select.


Since reading some peripheral registers has side effects (e.g. reading a data byte from a UART), it's not acceptable for the EMC to generate a spurious read from an address adjacent to the one I'm intending to read.


I've been fighting with this issue for a couple weeks now, and have been corresponding with our FAE, but have gotten nowhere.


If anybody has seen this issue (even if you don't know the solution) or has any ideas, please let me know.

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