lpcware

SDRAM corrupt data

Discussion created by lpcware Employee on Jun 15, 2016
Latest reply on Jun 15, 2016 by lpcware
Content originally posted in LPCWare by nohabviktor on Wed Nov 05 01:46:49 MST 2014
Hi!

I have a problem to SDRAM on my custom LPC1788 board.
The board has two 16 bit SDRAM on 32 bit data bus.
Two SDRAM not working in 32 bit mode, only one in 16 bit mode.
In 16 bit mode is works fine with 54Mhz and 108 Mhz EMC clock and run the linux kernel, but 32 bit mode two sdram is

not working.
In 32 bit mode the data is corrupt, memtest is fail, linux image is crc error if I downloaded by tftp.

I tried the memory timing incrase and decrase, but nothing changed.

The diff output:
The corrupt data different is always 2 byte in 2 Mbyte file:

39906c39906

< a009be00: 2500ebcb 0a0346a9 46a846a9 0f00f1ba    ...%.F...F.F....
---
> a009be00: 2500b004 0a03ebcb 46a846a9 0f00f1ba    ...%.....F.F....
62027c62027
< a00f2490: ffffffff ffffffff 00800000 0080ffff    ................
---
> a00f2490: ffffffff ffffffff 00800000 ffffffff    ................
62029c62029
< a00f24b0: 00000000 00000000 00000400 00000000    ................
---
> a00f24b0: 00000000 00000000 00000400 00000400    ................
62034c62034
< a00f2500: 00000000 00000000 00000000 00000000    ................
---
> a00f2500: 00000000 00000000 00000001 00000000    ................
62424c62424
< a00f3d60: 00000000 00000001 a00d86bd a00d868c    ................
---
> a00f3d60: 00000000 00000001 a00d8689 a00d86bd    ................
62579c62579
< a00f4710: a00fe7ec a00f0004 00000004 000001a4    ................
---
> a00f4710: a00d8b07 a00fe7ec 00000004 000001a4    ................
62701c62701
< a00f4eb0: ffffffff 00000000 98968000 98960008    ................
---
> a00f4eb0: ffffffff 00000000 98968000 00000008    ................
64149c64149
< a00fa930: ffffffff 00000000 00000000 00007461    ............at..
---
> a00fa930: ffffffff 00000000 00000000 74737461    ............atst


This is my memory init in u-boot:


/*
* Enable power on EMC
*/
lpc178x_periph_enable(LPC178X_SCC_PCONP_PCEMC_MSK, 1);

/*
* Clock delay for EMC
*/
LPC178X_SCC->emcdlyctl = ( 0x8 | (0x8 << 8) | (0x8 << 16) );

/*
* Enable EMC
*/
LPC178X_EMC->emcctrl = LPC178X_EMC_CTRL_EN_MSK;
/*
* Little-endian mode
*/
LPC178X_EMC->emccfg = 0;

...
...
...


/*
* Configure DRAM timing
*/
dy->rascas =
(3 << LPC178X_EMC_DYRASCAS_RAS_BITS) |
(3 << LPC178X_EMC_DYRASCAS_CAS_BITS);
LPC178X_EMC->dy_rdcfg =
(1 << LPC178X_EMC_DYRDCFG_RD_BITS);
LPC178X_EMC->dy_trp  = 1;
LPC178X_EMC->dy_tras = 2;
LPC178X_EMC->dy_srex = 3;
LPC178X_EMC->dy_apr  = 1;
LPC178X_EMC->dy_dal  = 5;
LPC178X_EMC->dy_wr   = 3;
LPC178X_EMC->dy_rc   = 3;
LPC178X_EMC->dy_rfc  = 3;
LPC178X_EMC->dy_xsr  = 3;
LPC178X_EMC->dy_rrd  = 0;
LPC178X_EMC->dy_mrd  = 3;

udelay(100000);



//32bit databus:
#ifdef CONFIG_SDRAM_32_BIT_DATABUS
      dy->cfg = (1u << 14) | (0u << 12) | (3u << 9) | (1u << 7);
#else
      dy->cfg = 0x0000680;
#endif




LPC178X_EMC->dy_ctrl = LPC178X_EMC_DYCTRL_CE_MSK | LPC178X_EMC_DYCTRL_CS_MSK |
(LPC178X_EMC_DYCTRL_I_NOP << LPC178X_EMC_DYCTRL_I_BITS);
udelay(200000);

LPC178X_EMC->dy_ctrl =
LPC178X_EMC_DYCTRL_CE_MSK | LPC178X_EMC_DYCTRL_CS_MSK |
(LPC178X_EMC_DYCTRL_I_PALL << LPC178X_EMC_DYCTRL_I_BITS);

LPC178X_EMC->dy_rfsh = 1;

udelay(1000);

LPC178X_EMC->dy_rfsh = 0x2E;
 
LPC178X_EMC->dy_ctrl =
LPC178X_EMC_DYCTRL_CE_MSK | LPC178X_EMC_DYCTRL_CS_MSK |
(LPC178X_EMC_DYCTRL_I_MODE << LPC178X_EMC_DYCTRL_I_BITS);

#ifdef CONFIG_SDRAM_32_BIT_DATABUS
tmp32 = *(volatile u32 *)(CONFIG_SYS_RAM_BASE | (0x32UL << 13));
#else
tmp32 = *(volatile u32 *)(CONFIG_SYS_RAM_BASE | (0x33UL << 12));
#endif

LPC178X_EMC->dy_ctrl = 0x0000;

/*
* Enable DRAM buffer
*/

//32bit databus:
#ifdef CONFIG_SDRAM_32_BIT_DATABUS
      dy->cfg = (1u << 14) | (0u << 12) | (3u << 9) | (1u << 7) | LPC178X_EMC_DYCFG_B_MSK;
#else
      dy->cfg = 0x0000680 | LPC178X_EMC_DYCFG_B_MSK; //1<<19
#endif



/*
* Fill in global info with description of DRAM configuration
*/
gd->bd->bi_dram[0].start = CONFIG_SYS_RAM_BASE;
gd->bd->bi_dram[0].size  = CONFIG_SYS_RAM_SIZE;

udelay(1000);


Please give me an advice on what could be the problem?

Outcomes