Piotr Fyda

Comments on TWR-K60D100, K60 and KSDK-1.3.0 documentation

Discussion created by Piotr Fyda on Mar 22, 2016

Hello NXP,

I have some comments on K60, TWR-K60D100 and KSDK- !1.3.0 documentation:

 

KSDK_1.3.0\examples\twrk60d100m\driver_examples    provide some code for SPI master and slave.

This does not work for SPI1 because:

 

  1. 1. Definition of SPI1 pins in pin_mux.c  is false

file ..\Freescale\KSDK_1.3.0\examples\twrk60d100m\pin_mux.c :

void configure_spi_pins(uint32_t instance) {

  switch(instance) {

    case SPI1_IDX:                       /* SPI1 */

      /* Affects PORTB_PCR10 register */

    PORT_HAL_SetMuxMode(PORTB,10u,kPortMuxAlt2);

    /* Affects PORTB_PCR17 register */

    PORT_HAL_SetMuxMode(PORTB,17u,kPortMuxAlt2);

    /* Affects PORTB_PCR11 register */

    PORT_HAL_SetMuxMode(PORTB,11u,kPortMuxAlt2);

    /* Affects PORTB_PCR16 register */

    PORT_HAL_SetMuxMode(PORTB,16u,kPortMuxAlt2);

 

It should be rather (TWRK60D100 has SPI1 on PTE1,2,3,4 !)

     PORT_HAL_SetMuxMode(PORTE,1u,kPortMuxAlt2);

     PORT_HAL_SetMuxMode(PORTE,2u,kPortMuxAlt2);

     PORT_HAL_SetMuxMode(PORTE,4u,kPortMuxAlt2);

     PORT_HAL_SetMuxMode(PORTE,3u,kPortMuxAlt2);

 

  1. 2. There is an error on sheet 4 of schematics of TWRK60D100M

pin     signal name in schematics            is in reality

D2     PTE1  SDHC0_D0/SPI1_SIN        SPI1_SOUT

E4     PTE3  SDHC0_D0/SPI1_SOUT    SPI1_SIN

This pinning is also defined in §10.3.1 of K60P144M100SF2V2RM Rev.2.

So the signals on the B-connector of the elevator are:

B7 - SPI1_CLK

B9 - SPI1_CS0

B10 - SPI1_SIN                   and not   SPI1_SOUT

B11 - SPI1_SOUT               and not   SPI1_SIN

Furthermore schematics of the Elevator uses signal names, which are not compatible with the K60 pinning and it results  in confusion:    SPIx_MISO and SPIx_MOSI

I suppose these abbreviations can be translated to Master_Input_Slave_Output and Slave_Output_Master_Input but in K60 a pin is either OUT or IN - same state for slave and master.

 

  1. 3. Quality of Reference Manual K60P144M100SF2V2RM Rev.2 Jun 2012

Some examples of concerning SPI (there are probably more problems related to other modules):

 

a) SPI versus DSPI

Throughout the first 1412 pages of manual (except for page 191 - table 5-2,  Module DSPI) only SPI is referenced.

On page 1412, in description for MDIS-bit, one read "When DSPI is used in Slave Mode..." - one can ask What is DSPI ?

From this point on, the manual speaks one time about SPI, another time about DSPI.

One can think: probably it's the same... but may be not ?

 

b) SPIx_MCR layout

§50.3.1, page 1410 shows  the SPIx_MCR layout where:

                bit 25 is ROOE and bits 24, 23, 22 are reserved

In the old manual (K60P144M100SF2RM Rev.6 Nov. 2011), there was:

                bit 25 was PCSSE , ROOE was on bit 24 and bits 23, 22 were reserved

Kinetis Desing Studio 3.1.0 shows in EmbSys Registers the "old" layout (MK60D10 chip selected) and ROOE seems to be really on bit 24 !

 

c) Frame size in slave receive mode

§50.3.4 Clock and Transfer Attributes Register (In Slave Mode) defines bits 31-27 as FMSZ - Frame size.

5 bits result in 0x1f=31 - so 32-bit frame should be possible (ie. data in 32-bit SPIx_POPR)

It is not !!

The highest bit of FMSZ has no function at all !

One can receive 32-bits but one has to read SPIx_POPR 2 times (2x 16-bit) what is completely undocumented in the manual.

 

d) §50.4.6 - Slave Mode Operation Constraints

One read there:

Received data is transferred to the receive buffer at last SCK edge of each frame, defined by frame
size
programmed to the CTAR0/1 register. Then the data from the buffer is transferred to the RXFIFO or DDR register.

Remarks:

  - frame size works only for frames up to 16-bits

  - for slave only CTAR0 can be used as §50.3.4 says

        When the module is configured as an SPI bus slave, the CTAR0 register is used.

  - "DDR" does not appear in the whole manual ! - what is it ???

 

e) §A.50 - DSPI chapter changes

Most of names listed in the second table (page 1799) do not appear in the K60P144M100SF2V2RM Rev.2 Jun 2012.

One read there for instance:    programmable serial frame size upto 64 bits...

This table is simply from another manual !!!

 

All this is somehow similar to quality of Kinetis SDK v.1.3 API Reference Manual Rev.0

see  https://community.freescale.com/thread/385338

 

Bravo NXP !  

Outcomes