I'm using 2 TLV320AIC3106 codecs (connected to SSI1 and SSI2) using MCLK from iMX6, and I need to change the SSI sampling rate (frame rate) from 44.1KHz to 48KHz.
In order to do that, the relevant PLL frequency (PLL4) should be changed from 632.2176 MHz to 688.128 MHz.
(Alternatively, SSI's sys clock should be changed from 11.2896 MHz to 12.288 MHz).
In which register, and in which source file is this done (perhaps /arch/arm/mach-mx6/clock.c, or is that relevant only for BCLK generation?)
i.e. I'm using kernel V3.0.35 if that makes a difference.