Where can I change SSI's sys clock (from 11.2896 MHz to 12.288 MHz)

[yehudastern]

Hi,

I'm using 2 TLV320AIC3106 codecs (connected to SSI1 and SSI2) using MCLK from iMX6, and I need to change the SSI sampling rate (frame rate) from 44.1KHz to 48KHz.

In order to do that, the relevant PLL frequency (PLL4) should be changed from 632.2176 MHz to 688.128 MHz.

(Alternatively, SSI's sys clock should be changed from 11.2896 MHz to 12.288 MHz).

In which register, and in which source file is this done (perhaps /arch/arm/mach-mx6/clock.c, or is that relevant only for BCLK generation?)

i.e.   I'm using kernel V3.0.35 if that makes a difference.

Thanks.

[igorpadykov · Accepted solution]

Hi Yehuda

one can add codes for reprogramming PLL using CCM_ANALOG_PLL_AUDIO_NUM,

CCM_ANALOG_PLL_AUDIO_DENOM at early initialization for example

mx6_sabresd_board_init() board-mx6q_sabresd.c

Best regards

igor

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[yehudastern]

Hi Igor,

Thanks for your reply.

I understood that in order to get a PLL output frequency of 688.128 MHz (= 24 MHz * 28.672), I should choose DIV_SELECT=28, NUM=84, DENOM=125.

But in which header file can I locate the following registers:

CCM_ANALOG_PLL_AUDIO_NUM, CCM_ANALOG_PLL_AUDIO_DENOM, and CCM_ANALOG_PLL_AUDIOn ?

Best regards

Yehuda

[igorpadykov]

Hi Yehuda

one can look at ...arch/arm/plat-mxc/include/mach/mx6.h

and add manually, if not found.

~igor

[yehudastern]

Hi Igor,

Thanks again.  It was really helpful.

I've added the relevant register addresses at ...arch/arm/mach-mx6/crm_regs.h (along with other PLL addresses) which all relate to a

macro defining the physical to virtual address mapping, located at mx6.h as you indicated.

After adding the bellow code at  mx6_xxx_som_board_init, the PLL was locked with the desired frequency.

*(volatile unsigned int*) PLL4_AUDIO_BASE_ADDR = 0x201C;     // DIV_SELECT=28, ENABLE=1, BYPASS=POWERDOWN=0

*(volatile unsigned int*) CCM_ANALOG_PLL_AUDIO_NUM = 84;

*(volatile unsigned int*) CCM_ANALOG_PLL_AUDIO_DENOM = 125;

Just last question:  isn't it possible to do the same by using the following function:  clk_set_rate(&pll4_audio_main_clk, 688128000) ?

If not, what is this function good for?

Best regards

Yehuda

[igorpadykov]

Hi Yehuda

clk_set_rate() selects frequencies already available in system

(not requiring pll reprogramming), they are given in clocks arrays

like pll4_audio_main_clk[] and others

~igor

[yehudastern]

BTW, what's the difference between the following registers:

- CCM_ANALOG_PLL_AUDIO          (addr:  0x020C8070)

- CCM_ANALOG_PLL_AUDIO_SET (addr:  0x020C8074)

- CCM_ANALOG_PLL_AUDIO_CLR (addr:  0x020C8078)

- CCM_ANALOG_PLL_AUDIO_TOG (addr:  0x020C807C)

Best regards

Yehuda

[yehudastern]

Hi Igor,

Although the PLL was locked with the desired frequency,  I still haven't managed to change the Serial bit clock from 1.4112 MHz to 1.536 MHz

Please refer to Table 61-7 in i.MX6 reference manual and the code below (added to mx6_xxx_som_board_init) and advise if there are additional registers that should be updated.

*(volatile unsigned int*) PLL4_AUDIO_BASE_ADDR = 0x10201C;           // DIV_SELECT=28, POST_DIV_DELECT=1, ENABLE=1, BYPASS=POWERDOWN=0

                                                                                                                    //  (PLL4_AUDIO_BASE_ADDR  is actually  CCM_ANALOG_PLL_AUDIO)

*(volatile unsigned int*) CCM_ANALOG_PLL_AUDIO_NUM = 84;            // NUM/DENOM = 84/125 = 0.672

*(volatile unsigned int*) CCM_ANALOG_PLL_AUDIO_DENOM = 125;     // PLL_OUT = 24 MHz * 28.672 = 688.128 MHz

*(volatile unsigned int*) MXC_CCM_CS1CDR = 0xEC10387;                    // SSI1_CLK_pred = 7, SSI1_CLK_podf = 8    (SSIDIV = 56)

*(volatile unsigned int*) MXC_CCM_CS2CDR = 0x073125B;                     // SSI2_CLK_pred = 2, SSI2_CLK_podf = 28  (SSIDIV = 56) 

*(volatile unsigned int*) MXC_CCM_CSCMR1 = 0xF0A802;                      // SSI1_CLK_sel, SSI2_CLK_sel, SSI3_CLK_sel => derived from PLL4

*(volatile unsigned int*) SSI1_STCCR = 0xE103;                                       // DIV2=PSR=0, WL=7 (=> 16 Bits/Word), DC=1, PM=3  

*(volatile unsigned int*) SSI1_SRCCR = 0xE103;                                       // DIV2=PSR=0, WL=7 (=> 16 Bits/Word), DC=1, PM=3

*(volatile unsigned int*) SSI2_STCCR = 0xE103;                                       // DIV2=PSR=0, WL=7 (=> 16 Bits/Word), DC=1, PM=3

*(volatile unsigned int*) SSI2_SRCCR = 0xE103;                                       // DIV2=PSR=0, WL=7 (=> 16 Bits/Word), DC=1, PM=3

Best regards

Yehuda