Hello Michael Roeder,
I am not aware of anyone trying on LS1 processors, there're such implementation on PA based processors.
There is FTF PPT by our engineer touched on this, which is available from:
https://www.nxp.com/webapp/Download?colCode=FTF12_NET_F0215PDF&location=null&fsrch=1&sr=2&pageNum=1&...
The basic ideas:
*May Lose external MDIO communication between the two MDC masters. Configuration and status info can be placed in system memory for access.
*Normal SGMII trace lengths should work up to 12". anything longer may need 1000Base-KX (which is not supported on any eTSEC based device even if it says it does).
*IBIS modeling is essential to confirm signal integrity across the interconnect.
Have a great day,
Lunmin
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