AnsweredAssumed Answered

i.MX6 “PHY link never came up”

Question asked by Josh Eckhoff on Jan 18, 2016
Latest reply on Nov 16, 2017 by Selami CANDAR

Periodically we are seeing an issue which causes the Wi-Fi to fail to load due to a PCI bus link issue.

 

The tell-tale sign of the issues is seeing the “PHY link never came up” message in the console output when booting. When this message is displayed the i.MX6 was unable to establish a link with the AW-CH397 WiFi module.

 

Device is a Custom board using the Variscite  VAR-SOM-MX6 http://www.variscite.com/products/system-on-module-som/cortex-a9/var-som-mx6-cpu-freescale-imx6

 

We began seeing a significant failure rate on the PCIe link initialization. After weeks of testing we were unable to triage the issue. Once the issue occurred on a board/SOM combo, it would often persist until that board and SOM were left alone (as if an environmental or temperature issue impacted it). Trying the same board and/or SOM a day later, and it would work.

 

A fix came across in uboot from Variscite concerning core voltage settings. This solved our problem at the time, and we no longer saw the link failures in a significant amount. Although they do still happen, just more sporadically and more often on specific boards.

Software and Core Voltages

Looking through Variscite’s commit history a commit to uboot was made regarding core voltages:

https://github.com/varigit/uboot-imx/commit/06fd56c8f6fe4d7781f9e72852f284f81542d0ff

https://github.com/varigit/uboot-imx/commit/05534a1e791699b365e8445819460ef6ceca5bf2

 

Applying these patches made the PCIe problem appear to go away. In reality the problem became less frequent but persisted.

 

Hardware and PHYs

The Freescale i.MX6 PCIe PHY is compatible to PCIe v2.0.

The Azurewave AW-CH397 PCIe PHY is compatible to PCIe v3.0. The Azurewave part is based on the Marvell 88W8897.

 

The Azurewave interface speed is 2.5Gbps so it only requires a PCIe v1.0 compatible link partner. Freescale

 

Signal Integrity and Impedance

The PCIe v3.0 recommended impedance range is 80-120 ohm differential. Freescale support person mentioned 85 ohms in the Freescale forum discussion below and in their Design guide, but Marvell mentions 100 ohms differential. Most importantly it was confirmed with Variscite that they routed their board at 100 ohms differential and so the Carrier Board was designed to match that.

 

Signal Integrity was measured with a high speed scope and discussed at length in the following two posts:

https://community.freescale.com/message/537250#537250

http://electronics.stackexchange.com/questions/180012/pcie-diagnosing-and-improving-an-eye-diagram

 

 

Initial investigation into the issue lead to posts on the internet with the same error message. Some contained suggest patches:

 

http://www.variscite.com/support-forum/viewtopic.php?t=109

 

diff --git a/drivers/pci/host/pci-imx6.c b/drivers/pci/host/pci-imx6.c

index 1c781f9..d7f1a40 100644

--- a/drivers/pci/host/pci-imx6.c

+++ b/drivers/pci/host/pci-imx6.c

@@ -442,7 +442,7 @@ static int imx6_pcie_wait_for_link(struct pcie_port *pp)

        int count = 200;

 

        while (!dw_pcie_link_up(pp)) {

-               udelay(100);

+               udelay(1000);

                if (--count)

                        continue;

 

Message was edited by: Josh Eckhoff

Outcomes