What is the correct procedure for changing the clock source for LDB_DI0_SERIAL_CLK_ROOT?
Currently we are showing startup image on LVDS display already in U-Boot. First we configure PLL5 to have needed frequency for LVDS interface (33MHz) and then set the mux (picture below) in reqister CS2CDR to use PLL5. However, occasionally in cold boot the LVDS interface does not drive any signal to the TFT panel. This jamming happens already in U-Boot. When the default clock source MMDC_CH1_AXI_CLK_ROOT is used the LVDS interface is not detected to fail, although then the clock frequency is incorrect for the TFT panel.
In reference manual is mentioned that for proper clock switching procedure both the current clock and the clock to be selected must remain active during the entire selection process. So could you provide a code or pseudo code, what is the correct setting sequence to select PLL5 for LDB_DI0_SERIAL_CLK_ROOT and LDB_DI0_IPU? U-Boot base is boundarydevices U-boot dated 25.3.2013.