IMX6, LDB_DI0_SERIAL_CLK_ROOT clock source change

[janiojala]

Hello,

What is the correct procedure for changing the clock source for LDB_DI0_SERIAL_CLK_ROOT?

Currently we are showing startup image on LVDS display already in U-Boot. First we configure PLL5 to have needed frequency for LVDS interface (33MHz) and then set the mux (picture below) in reqister CS2CDR to use PLL5. However, occasionally in cold boot the LVDS interface does not drive any signal to the TFT panel. This jamming happens already in U-Boot. When the default clock source MMDC_CH1_AXI_CLK_ROOT is used the LVDS interface is not detected to fail, although then the clock frequency is incorrect for the TFT panel.

In reference manual is mentioned that for proper clock switching procedure both the current clock and the clock to be selected must remain active during the entire selection process. So could you provide a code or pseudo code, what is the correct setting sequence to select PLL5 for LDB_DI0_SERIAL_CLK_ROOT and LDB_DI0_IPU? U-Boot base is boundarydevices U-boot dated 25.3.2013.

-Jani

[igorpadykov]

Hi Jani

for changing pll frequency procedure one can look at sect.18.5.1.6

Disabling / Enabling PLLs i.MX6DQ Reference Manual (rev.3  7/2015)

http://cache.freescale.com/files/32bit/doc/ref_manual/IMX6DQRM.pdf

and EB790 Configuration of Phase Fractional Dividers

http://cache.freescale.com/files/32bit/doc/eng_bulletin/EB790.pdf

Best regards

igor

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[janiojala]

Thanks Igor,

Thank you for the information. The linked documents refer mainly to PLL configuration which is important information. As the note in reference manual says "proper clock switching" procedures should be followed.

Does that mean that the MUX in this case should be set to use PLL5 after the PLL5 is enabled or should the mux be switched before enabling PLL5?

I have seen Linux patches for rather odd mux configuration sequence, as in discussion linked below.

[PATCH] ARM: imx6: Fix procedure to switch the parent of LDB_DI_CLK

And should the IPU/LDB be configured before or after clock enabling?

Kind regards,

-Jani

[igorpadykov]

Hi Jani

general procedure is to enable/lock pll then switch muxes

and enable modules. Referenced patch seems described some

special case.

Best regards

igor

[janiojala]

Hello Igor,

Still I would like to know how to switch from default clock source (MMDC_CH1_AXI_CLK_ROOT) to PLL5, without introducing a glitch to the divider? Please see the picture in the original post. It is mentioned in the reference manual that:

"The input clocks to the mux are required to be gated before switching the source clock in

the CCM clock mux and the output should also be gated. If the input and output clocks

are not gated, clock glitches can propagate to the logic that follows the clock mux,

causing the logic to behave unpredictably."

If I have understood correctly the default clock MMDC_CH1_AXI_CLK_ROOT is not gated. So how to handle "gating" since the default clock does not have a gate (CG)?

Kind regards,

-Jani

[igorpadykov · Accepted solution]

Hi Jani

one can look at Support-LVDS-clock-source-from-PLL5.patch

Patch to support uboot logo keep from uboot to kernel to Android for JB4.2.2_1.1.0-GA and L3.0.35_4....

~igor

[janiojala]

Hello Igor,

Thank you for your help. The default clock MMDC_CH1_AXI_CLK_ROOT change seemed to be the problem. In the patches, that you listed, is preformed a certain procedure for clock source change. If it is not done according to the patch LVDS interface may jam occasionally.

-Jani