Hello. I have question about ODT setting of DDR3 DQS in i.MX6DQ.
The ODT of DDR3 DQS can set at IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS*_P.
The DQS ODT setting was disabled in jb4.2.2_1.0.0.
i.MX6 SABRE SD isn't using ODT on DQS line, is it?
If one set the this register, does ODT become active to Write and Read?
(Or, is it active only at the time of Read operation?)