there are several posts about using the ENET-PLL to generate the 125MHz RGMII reference clock. But when doing this, I still need a crystal for the Ethernet PHY.
So I am considering using GPIO16 (mux configured for ENET_REF_CLOCK) as 25MHz clock output for the Gigabit-Ethernet PHY which itself provides the 125MHz reference clock for the RGMII.
A configuration like in Re: Using i.MX6 to generate 125MHz reference clock for RGMII interface with the different DIV_SELECT = 00 for the PLL should do it.
The voltage levels of GPIO16 and the PHY's clock input are compatible.
Are there any pitfalls I didn't see yet?
What about jitter - may this be a problem? I can't find further information about the PLL.