25MHz clock from i.MX 6 GPIO16?

[mahi]

Hi Community,

there are several posts about using the ENET-PLL to generate the 125MHz RGMII reference clock. But when doing this, I still need a crystal for the Ethernet PHY.

So I am considering using GPIO16 (mux configured for ENET_REF_CLOCK) as 25MHz clock output for the Gigabit-Ethernet PHY which itself provides the 125MHz reference clock for the RGMII.

A configuration like in Re: Using i.MX6 to generate 125MHz reference clock for RGMII interface  with the different DIV_SELECT = 00 for the PLL should do it.

The voltage levels of GPIO16 and the PHY's clock input are compatible.

Are there any pitfalls I didn't see yet?

What about jitter - may this be a problem? I can't find further information about the PLL.

Best regards

Martin

[weidong_sun · Accepted solution]

Hello, Martin,

    Many customer used this solution to provide clock to PHY, GPIO_16 can output 25MHz / 50MHz / 125MHz clock. Actually, you don't need to think more about jitter, the clock can ensure PHY to work normally.

    In addition, the high level of clock output from GPIO_16 is determined by NVCC_GPIO, so you should notice if it is compatible with that of PHY.

Regards,

Weidong