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About IPU specification.

Question asked by Takashi Takahashi on Jul 9, 2015
Latest reply on Jul 16, 2015 by Yuri Muhin

Hi community.

Our customer has 6 questions.

Would you please advice to me.

 

1, IPU is can ensure maximum 4Plane in DRAM.

    Is it correct understanding?

 

2,Two IPU block  with the maximum 2plane each?

   Each Plane can have System Memmory 2 Plane?

Or , 1Plane to the System Memory, as 1Plane to the output of the VDIC, also have a total 2Plane?

 

3,If each Plane will ultimately out put from DI,

  Is DI (DP?) synchronize LCD pixel clocks each Plane from the picture data, each block processes and synthesis done within one frame?

 

4,If each Plane will ultimately out put from DI,

When the DI is to transfer a picture of each Plane according to the drawing period of the LCD,

That way drawn(like some noise issues) to each Plane pictures may appear on the LCD?

 

5,IMX6DQ REF Manual  of  37.1.2.1.5.1 De-interlacing in the VDIC, Output: progressive frame Rate: up to 240 MP/sec

  but IMX6DQ RM of 37.4.11.7  VDIC Restrictions described on Maximum output pixel rate is 100 MP/s.

  Pixel rate of output value is different, How do i understand?

 

6,IMX6DQ Ref Manual of 37.1.2.1.4.2 Display Processor (DP)  is described Output: to display (through the DC), Rate: up to 240M pixels / sec ,

   But There is no described Rate for the input. Please tell me the specified value of the input Rate.

 

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